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Software

About: Software is a research topic. Over the lifetime, 130577 publications have been published within this topic receiving 2028987 citations. The topic is also known as: computer software & computational tool.


Papers
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Patent
29 Jun 1998
TL;DR: A reconfigurable processor chip as mentioned in this paper includes a standard processor, blocks of reconfigured logic (1101, 1103), and interfaces (319a, 319b, 311) between these elements.
Abstract: The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (1101, 1103), and interfaces (319a, 319b, 311) between these elements. The chip allows application code to be recompiled into a combination of software and reloadable hardware blocks using corresponding software tools. A mixture of arithmetic cells and logic cells allows for higher effective utilization of silicon than a standard interconnect. More efficient use of configuration stack memory results, since different sections of converted code require different portions of ALU functions and bus interconnect. Many types of interfaces with the embedded processor are provided, allowing for fast interface between standard processor code and configurable "hard-wired" functions.

286 citations

Posted Content
TL;DR: This document introduces the Graph Signal Processing Toolbox (GSPBox) a framework that can be used to tackle graph related problems with a signal processing approach and explains the structure and the organization of this software.
Abstract: This document introduces the Graph Signal Processing Toolbox (GSPBox) a framework that can be used to tackle graph related problems with a signal processing approach. It explains the structure and the organization of this software. It also contains a general description of the important modules.

286 citations

Journal ArticleDOI
TL;DR: This paper argues that modularization, the traditional technique intended to reduce interdependencies among components of a system, has serious limitations in the context of software development and builds on the idea of congruence, proposed in prior work, to examine the relationship between the structure of technical and work dependencies.
Abstract: The identification and management of work dependencies is a fundamental challenge in software development organizations. This paper argues that modularization, the traditional technique intended to reduce interdependencies among components of a system, is not a sufficient representation of work dependencies in the context of software development. We build on the idea of congruence proposed by Cataldo et al [10] to examine the relationship between the structure of technical and work dependencies and their impact on software development productivity. Our empirical evaluation of the congruence framework showed that when developers’ coordination patterns are congruent with their coordination needs, the resolution time of modification requests was, on average, reduced by 32%. Those findings highlight the importance of identifying the “right” set of product dependencies that drive the coordination requirements among software developers.

285 citations

Patent
25 Jan 1991
TL;DR: In this article, a networked system having a wide variety of applications and particularly applicable to facilities management systems has multiple levels of software in processing nodes, including a "features" processing level which communicates requests for data to a software object level containing databases of processes and attributes and database managers.
Abstract: A networked system having a wide variety of applications and particularly applicable to facilities management systems has multiple levels of software in processing nodes. The levels include a "features" processing level which communicates requests for data to a software object level containing databases of processes and attributes and database managers. The database managers in the software object level operate to provide data to the high level features in the same format. The software object level communicates with a hardware object level which also contains databases and database managers to mask differences between operational hardware units. By categorizing operational units by type, additional units of a known type can be added with only low level hardware object database changes. Adding units of a new type is facilitated by software changes confined to the lower level hardware and software objects, avoiding software changes at high level features. Individual software objects are tailored for typical types of inputs and output devices encountered by facilities management systems. Universal drive circuitry also provides applicability to a broad range of devices.

285 citations

Journal ArticleDOI
TL;DR: In this article, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements, and a scheduling technique based on the new instruction level power model is proposed.
Abstract: Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements. Significant points of difference have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above effects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the effectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been verified through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modification, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modified programs either improve or remain unchanged.

284 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20246
20235,523
202213,625
20213,455
20205,268
20195,982