Software portability

About: Software portability is a research topic. Over the lifetime, 8987 publications have been published within this topic receiving 164922 citations. The topic is also known as: portability.

Platform-independent profiling in a virtual execution environment

Abstract: Virtual execution environments, such as the Java virtual machine, promote platform-independent software development. However, when it comes to analyzing algorithm complexity and performance bottlenecks, available tools focus on platform-specific metrics, such as the CPU time consumption on a particular system. Other drawbacks of many prevailing profiling tools are high overhead, significant measurement perturbation, as well as reduced portability of profiling tools, which are often implemented in platform-dependent native code. This article presents a novel profiling approach, which is entirely based on program transformation techniques, in order to build a profiling data structure that provides calling-context-sensitive program execution statistics. We explore the use of platform-independent profiling metrics in order to make the instrumentation entirely portable and to generate reproducible profiles. We implemented these ideas within a Java-based profiling tool called JP. A significant novelty is that this tool achieves complete bytecode coverage by statically instrumenting the core runtime libraries and dynamically instrumenting the rest of the code. JP provides a small and flexible API to write customized profiling agents in pure Java, which are periodically activated to process the collected profiling information. Performance measurements point out that, despite the presence of dynamic instrumentation, JP causes significantly less overhead than a prevailing tool for the profiling of Java code. Copyright © 2008 John Wiley & Sons, Ltd.

Scalability, portability and predictability: the BSP approach to parallel programming

Abstract: General purpose parallel computing systems come in a variety of forms. We have various kinds of distributed memory architectures, shared memory multiprocessors, and clusters of workstations. New technologies may increase this range still further. Can one hope to design portable and scalable parallel software in the face of such architectural diversity? In this paper we show that it is indeed possible to produce fully portable parallel software which will run with highly efficient, scalable and predictable performance on any general purpose parallel architecture. The approach we describe is based on the bulk synchronous parallel (BSP) model of computation. The BSP model provides a simple, unified framework for the design and programming of all kinds of general purpose parallel systems. Over the last few years, a number of important research activities in algorithms and architectures have been pursued as part of this new approach to scalable parallel computing. In this paper we give some simple BSP algorithms and show how they can be expressed as programs. We also briefly describe some of the BSP programming language developments which are now being pursued.

A comparative analysis of basic pattern recognition techniques for the development of small size electronic nose

Abstract: In this paper, we propose the investigation and the realization of an artificial sensor system and an analysis system able to extract analytical information from odors, under the constraint of being suitable for miniaturization and portability. A sensor array was realized with a series of carbon black–polymer detectors. The lack of reproducibility of those sensors was compensated using a very flexible calibration and recognition tool based on neural networks. The training strategy used in this work, that performs better than derivative-based optimization techniques like standard back-propagation, permits a very low cost VLSI realization, necessary condition for deep miniaturization of the system. A comparative analysis of different pattern recognition approaches was performed in order to evaluate the suitability of this kind of neural networks, which allow deep computing circuit miniaturization. Moreover, we used dimensionality reduction techniques to decrease the computational complexity of the classification technique. The analyses carried out in this study could allow the development of a compact and self-contained electronic nose, in which the analysis system is directly embedded in the sensor device. This should permit to minimize the costs and to obtain better portability and performances.

A case for richer cross-layer abstractions: bridging the semantic gap with expressive memory

Abstract: This paper makes a case for a new cross-layer interface, Expressive Memory (XMem), to communicate higher-level program semantics from the application to the system software and hardware architecture. XMem provides (i) a flexible and extensible abstraction, called an Atom, enabling the application to express key program semantics in terms of how the program accesses data and the attributes of the data itself, and (ii) new cross-layer interfaces to make the expressed higher-level information available to the underlying OS and architecture. By providing key information that is otherwise unavailable, XMem exposes a new, rich view of the program data to the OS and the different architectural components that optimize memory system performance (e.g., caches, memory controllers). By bridging the semantic gap between the application and the underlying memory resources, XMem provides two key benefits. First, it enables architectural/system-level techniques to leverage key program semantics that are challenging to predict or infer. Second, it improves the efficacy and portability of software optimizations by alleviating the need to tune code for specific hardware resources (e.g., cache space). While XMem is designed to enhance and enable a wide range of memory optimizations, we demonstrate the benefits of XMem using two use cases: (i) improving the performance portability of software-based cache optimization by expressing the semantics of data locality in the optimization and (ii) improving the performance of OS-based page placement in DRAM by leveraging the semantics of data structures and their access properties.