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Software portability

About: Software portability is a research topic. Over the lifetime, 8987 publications have been published within this topic receiving 164922 citations. The topic is also known as: portability.


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Book
03 Mar 1995
TL;DR: Software Reuse: A Decade-Long Experiment Libraries, File and Portability Configuration Management Base Tools: KSH and Easel APP - An Annotation Preprocessor for C Reverse Engineering-CIA Security and Software Engineering A Software Fault Tolerance Platform Generalized Event - Action Handling Software Process - Provence Inter-Tool Connections Evaluation of Approach.
Abstract: Software Reuse: A Decade-Long Experiment Libraries, File and Portability Configuration Management Base Tools: KSH and Easel APP - An Annotation Preprocessor for C Reverse Engineering-CIA Security and Software Engineering A Software Fault Tolerance Platform Generalized Event - Action Handling Software Process - Provence Inter-Tool Connections Evaluation of Approach.

42 citations

Proceedings Article
01 Jan 2005
TL;DR: The results show a 6X decrease in performance and a 100X increase in hardware resource usage for the virtual FPGA approach compared to mapping the circuits directly to a physical FFPA.
Abstract: Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures, yielding software portability benefits Researchers previously introduced the concept of a standard hardware binary to achieve similar portability benefits for hardware, using a JIT compiler to compile the hardware binary to an FPGA The JIT compiler includes lean versions of technology mapping, placement, and routing algorithms that implement the standard hardware binary on a simple custom FPGA fabric designed specifically for JIT compilation While developing a custom FPGA may be feasible for some applications, we propose implementing the simple FPGA fabric as a virtual FPGA In this paper, we present a virtual FPGA, described using structural VHDL and thus representing a firm core that a designer can synthesize onto an existing FPGA We synthesized the firm-core virtual FPGA onto Xilinx Spartan physical FPGAs and then mapped 18 benchmark circuits onto the virtual FPGA Our results show a 6X decrease in performance and 100x more hardware resource usage, for the virtual FPGA approach compared to mapping the circuits directly to the physical FPGA fabric While the hardware overhead is large, large commercial FPGA capacities may still mean that some applications can utilize a virtual FPGA approach if portability is more important than resource utilization Furthermore, our work provides a baseline for future virtual FPGA approaches that may reduce the performance or area overhead through various means

42 citations

Book ChapterDOI
06 Oct 2002
TL;DR: Jinline makes it possible to inline a method body before, after, or instead of occurrences of language mechanisms within a method, providing appropriate high-level abstractions for fine-grained alterations while offering a good expressive power and a great ease of use.
Abstract: Altering the semantics of programs has become of major interest. This is due to the necessity of adapting existing software, for instance to achieve interoperability between off-the-shelf components. A system allowing such alterations should operate at the bytecode level in order to preserve portability and to be useful for pieces of software whose source code is not available. Furthermore, working at the bytecode level should be done while keeping high-level abstractions so that it can be useful to a wide audience. In this paper, we present Jinline, a tool that operates at load time through bytecode manipulation. Jinline makes it possible to inline a method body before, after, or instead of occurrences of language mechanisms within a method. It provides appropriate high-level abstractions for fine-grained alterations while offering a good expressive power and a great ease of use.

42 citations

Book ChapterDOI
08 Jul 2001
TL;DR: This paper formulates and investigates the question of whether a given algorithm can be coded in a way efficiently portable across machines with different hierarchical memory systems, modeled as a(x)-HRAMs (Hierarchical RAMs), and proposes the decomposition-tree memory manager and the reoccurrence-width memory manager.
Abstract: This paper formulates and investigates the question of whether a given algorithm can be coded in a way efficiently portable across machines with different hierarchical memory systems, modeled as a(x)-HRAMs (Hierarchical RAMs), where the time to access a location x is a(x). The width decomposition framework is proposed to provide a machine-independent characterization of temporal locality of a computation by a suitable set of space reuse parameters. Using this framework, it is shown that, when the schedule, i.e. the order by which operations are executed, is fixed, efficient portability is achievable. We propose (a) the decomposition-tree memory manager, which achieves time within a logarithmic factor of optimal on all HRAMs, and (b) the reoccurrence-width memory manager, which achieves time within a constant factor of optimal for the important class of uniform HRAMs. We also show that, when the schedule is considered as a degree of freedom of the implementation, there are computations whose optimal schedule does vary with the access function. In particular, we exhibit some computations for which any schedule is bound to be a polynomial factor slower than optimal on at least one of two sufficiently different machines. On the positive side, we show that relatively few schedules are sufficient to provide a near optimal solution on a wide class of HRAMs.

42 citations

Patent
01 Oct 1996
TL;DR: In this article, the authors proposed a method for updating two-tiered databases in a telecommunications system which support local number portability through call connection information sets stored on the databases. But this method requires the second-tier databases to accept the set as an update, a new set or reject.
Abstract: This invention provides a means and method for updating two-tiered databases in a telecommunications system which support local number portability through call connection information sets stored on the databases. Pro-active updating is accomplished by tracking location, time and frequency of each switch querying the first tier centralized database for each stored call connection information set. At the time an update is made to a call connection information set at the first tier database, the set is offered to all second tier databases supporting individual switches which have queried the centralized database for that set. Second tier databases accept the set as an update, a new set or reject. Acceptance of a new set or rejection is dependent upon the set achieving a ranking based on recency and frequency of query above the threshold for storage. The second tier databases provide confirmation of set acceptance and rejection to the first tier database.

42 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20241
2023580
20221,257
2021290
2020308
2019381