Showing papers on "Spice published in 1985"
TL;DR: In this article, a general multiple coupled line model compatible with standard CAD programs, such as SPICE, is presented, which can be used to analyze and design coupled line circuits with linear, as well as nonlinear/time varying terminations, and to help study the pulse propagation characteristics in high-speed digital circuits.
Abstract: A general multiple coupled line model compatible with standard CAD programs, such as SPICE, is presented. It is shown that the model can be used to help analyze and design coupled line (e.g., microstrip) circuits with linear, as well as nonlinear/time varying terminations, and to help study the pulse propagation characteristics in high-speed digital circuits.
132 citations
TL;DR: An automated system has been developed to obtain the process statistical variations and extract SPICE model parameters for a large number of MOS devices, and a linear approximation for the yield body boundary is used to make an accurate prediction of parametric yield.
Abstract: Large statistical variations are often found in the performance of VLSI circuits; as a result, only a fraction of the circuits manufactured may meet performance goals An automated system has been developed to obtain the process statistical variations and extract SPICE model parameters for a large number of MOS devices Device length and width, oxide capacitance, and flat-band voltage are shown to be the principal process factors responsible for the statistical variation of device characteristics Intradie variations are much smaller than the interdie variations, therefore, only the interdie variations are responsible for variations in circuit performance This accurate and simple statistical modeling approach uses only four statistical variables, and thus enables the development of a very computationally efficient statistical parametric yield estimator (SPYE) A linear approximation for the yield body boundary is used to make an accurate prediction of parametric yield With the addition of temperature and supply voltage as operating condition variables, a maximum of seven simulations are required; only slightly more than the three to five required for "worst case analysis" The method has also been adapted statistical parametric specification of standard cells; performance ranges of circuit building blocks can be characterized once the statistical variations of process-dependent parameters are known Predicted performance variations from SPYE have been compared with measured variations in delay and power consumption for a 7000-gate n-MOS inverter chain Agreement with the mean delay and power are better than 5 percent where SPICE model parameters were obtained from the same slice used for circuit characterization Excellent agreement was obtained in the predicted spread in the circuit delay and power consumption using measured variations in the statistical variables
98 citations
TL;DR: The application of a popular and widely available electrical circuit simulation program called SPICE to modeling the electrical behavior of neurons with passive membrane properties and arbitrarily complex dendritic trees is described and extremely accurate transient calculations may be obtained.
Abstract: We describe the application of a popular and widely available electrical circuit simulation program called SPICE to modeling the electrical behavior of neurons with passive membrane properties and arbitrarily complex dendritic trees. Transient responses may be calculated at any location in the cell model following current, voltage or conductance perturbations at any point. A numbering method is described for binary trees which is helpful in transforming complex dendritic structures into a coded list of short cylindrical dendritic segments suitable for input to SPICE. Individual segments are modeled as isopotential compartments comprised of a parallel resistor and capacitor, representing the transmembrane impedance, in series with one or two core resistors. Synaptic current is modeled by a current source controlled by the local membrane potential and an "alpha-shaped" voltage, thus simulating a conductance change in series with a driving potential. Extensively branched test cell circuits were constructed which satisfied the equivalent cylinder constraints (Rall 1959). These model neurons were perturbed by independent current sources and by synaptic currents. Responses calculated by SPICE are compared with analytical results. With appropriately chosen model parameters, extremely accurate transient calculations may be obtained. Details of the SPICE circuit elements are presented, along with illustrative examples sufficient to allow implementation of passive nerve cell models on a number of common computers. Methods for modeling excitable membrane are presented in the companion paper (Bunow et al. 1985).
98 citations
TL;DR: Interdie variations in length and width, oxide capitance, and flat band voltage are shown to be responsible for process induced variations in circuit performance, which is the basis for SPYE, Statistical Parametric Yield Estimator.
Abstract: Large statistical variations are often found in the performance of VLSI circuits; as a result, only a fraction of the circuits manufactured may meet performance goals. An automated system has been developed to obtain the process statistical variations and extract SPICE model parameters for a large number of MOS devices. Device length and width, oxide capacitance, and flat-band voltage are shown to be the principal process factors responsible for the statistical variation of device characteristics. Intradie variations are much smaller than the interdie variations, therefore, only the interdie variations are responsible for variations its circuit performance. This accurate and simple statistical modeling approach uses only four statistical variables, and thus enables the development of a very computationally efficient statistical parametric yield estimator (SPYE). A linear approximation for the yield body boundary is used to make an accurate prediction of parametric yield. With the addition of temperature and supply voltage as operating condition variables, a maximum of seven simulations are required; only slightly more than the three to five required for "worst case analysis". The method has also been adapted statistical parametric specification of standard cells; performance ranges of circuit building blocks can be characterized once the statistical variations of process-dependent parameters are known. Predicted performance variations from SPYE have been compared with measured variations in delay and power consumption for a 7000-gate n-MOS inverter chain. Agreement with the mean delay and power are better than 5 percent where SPICE model parameters were obtained from the same slice used for circuit characterization. Excellent agreement was obtained in the predicted spread in the circuit delay and power consumption using measured variations in the statistical variables.
56 citations
01 Jan 1985
31 citations
TL;DR: In this paper, a device model that predicts large-signal GaAs MESFET performance has been implemented on the large-scale circuit simulation program SPICE, taking into consideration drift velocity saturation, channel length modulation, and subthreshold current effects.
Abstract: A device model that predicts large-signal GaAs MESFET performance has been implemented on the large-scale circuit simulation program SPICE. The model takes into consideration drift velocity saturation, channel length modulation, and subthreshold current effects. In addition, the model depends primarily on physical (i.e. material and geometric) rather than empirical parameters. Combined with the SPICE program, a general CAD tool is formed which can be used to aid in the design of GaAs circuits such a power amplifiers, oscillators, mixers, and fast-switching digital integrated circuits. Model predictions are compared to measured device performance, and limitations of this large-signal circuit design approach are discussed.
27 citations
TL;DR: This program is a preprocessor to the program SPICE and processes hierarchicaly described circuits (subcircuits) and takes into account the following faults: • - floating gates • - open circuits and partially open circuits • - short circuits and partly short circuits.
18 citations
Patent•
20 Nov 1985
TL;DR: In this article, a process for preparing a naturally flavored and colored oleresin spice edible oil extract by contacting ground spice with fortified edible oil to extract flavor and color from the spice followed by pressure separation and blending the extracted spice residue with fresh oil to form a fortified oil containing spice color and flavor for recycling.
Abstract: A process is provided for preparing a naturally flavored and colored oleresin spice edible oil extract by contacting ground spice with fortified edible oil to extract flavor and color from the spice followed by pressure separation and blending the extracted spice residue with fresh oil to form a fortified oil containing spice color and flavor for recycling in the extraction process.
14 citations
TL;DR: In this article, a vertically integrated device modeling technique for GaAs IC's is presented for use in circuit simulation, where most of the SPICE2 capability can be utilized for modeling the gate transit time and parasitic effects.
Abstract: A vertically integrated device modeling technique for GaAs IC's is presented for use in circuit simulation. Most of the SPICE2 capability can be utilized for modeling the gate transit time and parasitic effects. A computer program has also been developed to extract model parameters from the measured device data.
10 citations
04 Jun 1985
TL;DR: In this paper, a general multiple coupled line model compatible with standard CAD programs, such as SPICE, is presented, which can be used to analyze and design coupled line circuits with linear, as well as non-linear/time varying terminations, and to study the pulse propagation characteristics in high speed digital and optical circuits.
Abstract: A general multiple coupled line model compatible with standard CAD programs, such as SPICE, is presented. It is shown that the model can be used to help analyze and design coupled line (e.g., microstrip) circuits with linear, as well as non-linear/ time varying terminations, and to help study the pulse propagation characteristics in high speed digital and optical circuits.
TL;DR: Results demonstrate that the popular p-i-n FET transimpedance amplifier is adversely sensitive to FET transconductance variations and distorts the pulse reponse, whereas the distributed gain and dual feedback design is substantially independent of transistor parameters and free of pulse distortion.
Abstract: Two conceptually different p-i-n FET receiver circuit architectures are evaluated using a SPICE circuit simulation. The popular p-i-n FET transimpedance amplifier is compared to a new architecture that uses distributed gain and dual feedback. To highlight the importance of circuit architecture to receiver performance, identical device parameters are used in each circuit model. Frequency, phase, and pulse responses are computed and presented in graphical form. Results demonstrate that the popular receiver is adversely sensitive to FET transconductance variations and distorts the pulse reponse, whereas the distributed gain and dual feedback design is substantially independent of transistor parameters and free of pulse distortion.
TL;DR: An MOS depletion device model that is compatible with SPICE circuit simulation program and based on device physics is described, and more accurate results compared to the empirical model are obtained.
Abstract: An MOS depletion device model that is compatible with SPICE circuit simulation program and based on device physics is described. The depletion device is modeled by an equivalent circuit consisting of various well-characterized semiconductor devices, for example, the enhancement MOS device and the JFET. IT has the advantages of both the existing physical and empirical models. The model is applicable to immediate circuit simulation and device fabrication. Derivation of the model along with its parameters for the Gaussian impurity distribution is given. Implementation of circuit simulation with SPICE is demonstrated. More accurate results compared to the empirical model are obtained.
Patent•
[...]
12 Jan 1985
TL;DR: In this article, a water-miscible organic solvent containing a specific amount of water in the presence of cyclodextrin was used to extract a natural spice such as sage, thyme, etc.
Abstract: PURPOSE:To obtain a spice extract having excellent flavor, palatability, storage stability, etc., by extracting a natural spice with a water-miscible organic solvent containing a specific amount of water in the presence of cyclodextrin. CONSTITUTION:A natural spice such as sage, thyme, etc. is extracted with water or a water-miscible organic solvent such as methanol, ethanol, etc. having a water-content of >= about 20wt% in the presence of cyclodextrin to obtain an aqueous extract of spice rich in the characteristic and excellent flavor and taste of natural spice without causing the deterioration and degradation of the flavor and taste.
06 Nov 1985
TL;DR: A circuit simulator program that completely characterizes the electrical performance of room-temperature digital integrated circuits (ICs) and provides small-signal frequency domain analysis, noise analysis, and transient behavior of lowtemperature analo readout devices.
Abstract: Because the interfacelmultiplexing circuitry in hybrid infrared (IR) focal plane arrays (FPAs) has become so complex, a computer-based modular analysis program is needed to evaluate these circuits for sensor applications. available for design studies of logic, layout, and circuit performance for room-temperature digital integrated circuits (ICs). Our need is for a circuit simulator program that completely characterizes the electrical performance, i.e., that provides small-signal frequency domain analysis, noise analysis, and transient behavior of lowtemperature analo readout devices. We selected the SPICE program? and implemented major modifications resulting from the severe numerical convergence requirements introduced by the cryogenic operating conditions and low current and voltage levels
TL;DR: Results demonstrate that the popular p-i-n FET transimpedance amplifier is adversely sensitive to FET transconductance variations and distorts the pulse reponse, whereas the distributed gain and dual feedback design is substantially independent of transistor parameters and free of pulse distortion.
Abstract: Two conceptually different p-i-n FET receiver circuit architectures are evaluated using a SPICE circuit simulation. The popular p-i-n FET transimpedance amplifier is compared to a new architecture that uses distributed gain and dual feedback. To highlight the importance of circuit architecture to receiver performance, identical device parameters are used in each circuit model. Frequency, phase, and pulse responses are computed and presented in graphical form. Results demonstrate that the popular receiver is adversely sensitive to FET transconductance variations and distorts the pulse reponse, whereas the distributed gain and dual feedback design is substantially independent of transistor parameters and free of pulse distortion.
01 Jan 1985
TL;DR: The SPICE-2, the circuit simulation program, is modified by incorporating a partition scheme with which a large circuit can be decomposed into several smaller but cascaded subcircuits, and each subcircuit is simulated separately in sequence with the outputs of the preceding sub Circuits to be the inputs of the next succeeding subCircuit.
Abstract: SPICE-2, the circuit simulation program, is modified by incorporating a partition scheme with which a large circuit can be decomposed into several smaller but cascaded subcircuits, and each subcircuit is simulated separately in sequence with the outputs of the preceding subcircuit to be the inputs of the next succeeding subcircuit. This effectively changes the SPICE-2 which is a time incremental circuit simulator into a time waveform circuit simulator. Examples of circuits simulated by this SPICE-2P show significant savings on the simulation time (up to 50%) and the memory utilized (up to 80%). The loading effect introduced due to the circuit partitioning is also studied. A simple model for the loading effect is used and implemented in the program. Less than 5% of error on the simulated waveforms are usually obtained.
TL;DR: In this paper, a DRO memory cell using three Josephson junctions has been devised whose operation depends only on the ratio of critical currents and application of the proper read/write voltages.
Abstract: A destructive read-out (DRO) memory cell using three Josephson junctions has been devised whose operation depends only on the ratio of critical currents and application of the proper read/write voltages. The effects of run-to-run and across-the-wafer variations in I c are minimized since all three junctions for a given cell are quite close to each other. Additional advantages are: immunity from flux trapping, high circuit density, and fast switching. Since destructive read-out is generally undesirable, a self-rewriting scheme is necessary. Rows and columns of cells with drivers and sense circuits, as well as small memory arrays and decoders have been simulated on SPICE. Power dissipation of cells and bias circuits for a 1K-bit RAM is estimated at about 2 mW. Inclusion of peripheral circuitry raises this by as much as a factor of five depending on the driving scheme and speed desired. Estimated access time is appreciably less than a nanosecond. Preliminary experimental investigations are reported.