Showing papers on "Spice published in 1988"

DELIGHT.SPICE: an optimization-based system for the design of integrated circuits

Abstract: DELIGHT.SPICE is the union of the DELIGHT interactive optimization-based computer-aided-design system and the SPICE circuit analysis program. With the DELIGHT.SPICE tool, circuit designers can take advantage of recent powerful optimization algorithms and a methodology that emphasizes designer intuition and man-machine interaction. Designer and computer are complementary in adjusting parameters of electronic circuits automatically to improve their performance criteria and to study complex tradeoffs between multiple competing objectives, while simultaneously satisfying multiple-constraint specifications. The optimization runs much more efficiently than previously because the SPICE program used has been enhanced to perform DC, AC, and transient sensitivity computation. Industrial analog and digital circuits have been redesigned using this tool, yielding substantial improvement in circuit performance. >

Simulation of MOSFET lifetime under AC hot-electron stress

Abstract: A substrate current model and a quasistatic hot-electron-induced MOSFET degradation model have been implemented using the Substrate Current And Lifetime Evaluator (SCALE) package. It is shown that quasistatic simulation is valid for a class of waveforms that includes those encountered in inverter-based logic circuits. The validity and limitations of the model are illustrated with experimental results. SCALE is linked to SPICE externally in a pre- and postprocessor fashion to form an independent simulator. The preprocessor interprets the input deck and requests SPICE to output the transient node voltages of the user-selected devices. The postprocessor then calculates the transient substrate current and makes a lifetime prediction. >

Mixed-Mode PISCES-SPICE Coupled Circuit and Device

Abstract: A computer program has been written to allow simulta- neous solution of an electrical network containing both nonlinear cir- cuit elements and two-dimensional finite element solid-state models. The circuit solver is based upon the popular SPICE-I1 (l) program, while the PISCES-I1 (2) program is used to model the solid-state de- vices. Both steady-state dc and time-dependent solutions are possible. Additional features have also been added to the solid-state model. These include photogeneration and the optional use of cylindrical coordi- nates.

Mixed-mode PISCES-SPICE coupled circuit and device solver

Abstract: A computer program has been written to allow simultaneous solution of an electrical network containing both nonlinear circuit elements and two-dimensional finite-element solid-state models. The circuit solver is based on the popular SPICE-II program, while the PISCES-II program is used to model the solid-state devices. Both steady-state DC and time-dependent solutions are possible. Additional features have also been added to the solid-state model, including photogeneration and the optional use of cylindrical coordinates. >

PWM conductance control

Abstract: Conductance (or current) control of switching regulators generally uses peak or hysteresis (e.g. LC/sup 3/) controllers, the advantages and problems of which have been widely reported. The behavior of a simple conventional pulsewidth-modulated (PWM) conductance control principle that has been used on space programs is described and analyzed. The chief advantage of the approach is that conventional integrated circuits and design techniques can be used, simplifying the designer's task. The design equations have been verified by both SPICE simulation and test results. >

Explicit formulation of delays in CMOS data paths

Abstract: An explicit formulation of the transient response of general combinational CMOS structures is presented, including load conditions and driving waveforms. Based on data-path decomposition in unidirectional elementary cells, timing models developed here allow an analytic formulation of the real temporal behaviour of inverters, transmission gate arrays, and general CMOS gates. Validation is obtained through a comparison between delay times, calculated following this formulation, and values deduced from SPICE simulations, for a large range of inverters and gate structures with different configuration ratios and tapering factors. Results are shown to be in excellent agreement with less than 10% discrepancy. >

Modelling and simulation of power mosfet's and power diodes

Abstract: A model of the power Mosfet is modified, improved and implemented into SPICE. A method for parameter extraction from electrical measurements is developed. The simulation results show a good agreement with t he measurements. The model considered is simple and accurate. The switching behavior of Mosfet's was simulated and analyzed. The parasitic oscillation in parallel circuits has been investigated. A favorable solution to avoid this undesirable effect is proposed and proved. A fundamental study was carried out to develop a new electric-analyti cal model for the PIN power diode. The internal processes d uring s witching were investigated by using physical device simulation. For the dide model a one-dimensicnal solution was derived. This solution includes the static and the dynamic behavior with the reverse recovery effect and high current effects. The simulations correlate well with the measurements.

Modelling and simulation of power MOSFETs and power diodes

Abstract: A model of a power MOSFET has been improved and implemented in SPICE. A method for parameter extraction from electrical measurements has been developed. The model is simple and accurate, and the simulation results show good agreement with the measurements. The switching behavior of the MOSFETs has been simulated and analyzed, and the parasitic oscillation in parallel circuits has been investigated. A way to avoid this undesirable effect is proposed and proved. The development of an electrical analysis model for the p-i-n power diode is reported. The internal processes during switching have been investigated using physical device simulation, and a one-dimensional solution has been obtained. >

A simple SPICE model for coupled transmission lines

Abstract: An exact model of a lossless multiconductor transmission line (MTL) is presented. The model is directly implementable in the SPICE code. It is therefore more readily available for use than a specially designed FORTRAN code. It is also an exact solution of the MTL equations, whereas most specially designed time-domain FORTRAN codes are approximate solutions. Implementation of the model in a SPICE code allows the incorporation of nonlinear terminations already present in SPICE. Therefore, a wide variety of electronic-circuit design problems can be investigated, and the actual crosstalk in a particular conductor interconnection pattern can be investigated. The model is suitable for use in the personal computer versions of SPICE; the predictions were obtained on an IBM PC AT using the demo version of PSPICE. >

SPICE models for power MOSFETs: an update

Abstract: Five existing power MOSFET models intended for use with SPICE simulations are reviewed and compared. Methods used for simulating the gate-drain capacitance are evaluated. The internal JFET employed in two of the models is found to be usually unnecessary. A simple two-value capacitance model is recommended. The performance of this model is demonstrated with data obtained from 200 kHz forward converter. >

Performance of fast monolithic ECL voltage comparators in constant-fraction discriminators and other timing circuits

Abstract: Timing errors caused by voltage comparator operation are investigated in detail for constant-fraction discriminators and other timing circuits. These errors result from changing comparator response time for input signals with different slopes (voltage/time) and different levels. Comparator response time is analyzed for a modern high-speed ECL voltage comparator using the SPICE circuit analysis program, which models the complex nonlinearities present in comparator operation. The simulated response time for a -90-mV to 10-mV step input is slightly larger than the specified comparator performance, indicating a conservative analysis. Response time is presented for a variety of input signals and supports a comparator response-time model that consists of a charge-sensitivity (variable-time) delay component and a fixed-delay component SPICE circuit simulation is extended to simulate comparator operation in a constant-fraction discriminator circuit. >

Delay analysis for BiCMOS drivers

Abstract: Simple delay models are derived for the different regions of operation for the bipolar transistors in a BiCMOS driver. The delay equations are approximate but extremely useful in relating the gate delay to the device and circuit parameters. Simulations from a mixed-level circuit and device simulator, CODECS, are used to verify the delay models. SPICE simulations are inadequate since high-level injection effects critical to the performance of the bipolar transistors are not well modeled with present bipolar transistor models in SPICE. The effects of various collector doping concentrations and epi-layer thickness are also investigated. >

Extraction of BJT model parameters using optimization method

Abstract: A method for parameter extraction of a SPICE 2G.6 bipolar junction transistor (BJT) model is presented. The proposed approach consists of minimizing a nonlinear objective function to produce a least-squares fit of the model equations to a set of measured device characteristics. All parameters are extracted using a combination of the direct-search optimization method and the variable metric algorithm. This makes it possible to obtain satisfactory results even in the presence of redundant parameters and poor initial values. A special strategy of calculating an objective function during optimization that requires very little CPU time is proposed. An example of parameter extraction of the SPICE 2 G.6 BJT model shows poor model accuracy. Therefore a model modification that gives a very good fit to the measured data is proposed. >

A GaAs MESFET large-signal circuit model for nonlinear analysis

Abstract: A large-signal GaAs MESFET model for performing nonlinear microwave simulations with SPICE or the Microwave SPICE and Libra programs is described. The model includes accurate analytical representation of the dependence of DC transconductance, gate-to-source capacitance, gate-to-drain capacitance, input and noise resistances, and drain-to-source resistance on operating gate-to-source and drain-to-source voltages. The model also functions as a master linear model that accurately replicates measured microwave S-parameters at arbitrarily chosen bias points within the transistor's useful operating C-V range. Microwave SPICE harmonic distortion simulations with the model compare favorably with measurements for an NEC NE71000 GaAs MESFET. >

S-parameter output from the SPICE program

Abstract: A procedure is presented to evaluate the S-parameters of a circuit using any generic or modified version of SPICE without making any modifications in SPICE internally. This method is qualified for a two-port network; however, the concept can be extended for an n-port network also. It is also generalized for analyzing any circuit with input, output, and ground terminals. >

Simulation of optically injection-locked microwave oscillators using a novel SPICE model

Abstract: Optical injection-locking of GaAs field-effect transistor microwave oscillators has been examined experimentally as well as by using two different optical interaction models. An additional simulation program with IC emphasis (SPICE) circuit for observing small locking ranges is also described. This first-order interaction model which utilizes a standard version of SPICE produces predictions of injection-locking range in excellent agreement with measured results. These tools allow the oscillator designer to optimize the injection-locking performance by analyzing various circuit topologies and DC bias levels. >

SPICE implementation of lossy transmission line and Schottky diode models

Abstract: The author describes models for the lossy transmission line and the Schottky diode that are incorporated into the source code of the circuit simulation program SPICE (version 2G.6). The model used for the lossy transmission line was derived by A.J. Gruodis (1979). The DC model for the Schottky barrier diode as shown was formulated by D.B. Estreich (1983). Examples used to verify the models are given. >

Equivalent circuit models of switches for SPICE simulation

Abstract: An equivalent circuit model of a switch consisting of controlled sources and LTI resistors which are SPICE-acceptable circuit elements is presented Based upon the model a SPICE input file of switched circuits can be written to perform both transient and steady-state analysis

High-voltage device modeling for SPICE simulation of HVIC's

Abstract: A novel methodology for flexible SPICE implementation of physical models for high-voltage power devices, accounting for their unique characteristics, is presented and demonstrated. The implementation is achieved without modifying the simulator code by utilizing user-defined controlled sources that reference a subroutine that defines the system of model equations. The simultaneous solution of the equations, which describe the integrated charges in the device and the quasistatic terminal currents in the terms of the terminal voltages, is effected by the SPICE2 nodal analysis. The methodology is exemplified by modeling the insulated-gate transistor (IGT). SPICE simulations of DC and transient characteristics of IGT switching circuits are discussed and shown to be representative of measurements. The flexibility of the modeling methodology for high-voltage integrated-circuit (HVIC) CAD is demonstrated by simulating effects of both static and dynamic latch-up in the merged bipolar/MOS structure of the IGT. >

Accurate analog modeling of short channel FETs based on table lookup

Abstract: A table lookup model for MOSFETs has been implemented in SPICE 3, to overcome the inadequacies of analytical models that are unable to represent short-channel effects. The model comprises a 2-D main table, a coarse 3-D subtable to incorporate substrate effects, and a table to interpolate between channel lengths. There are 370 data points stored. The tables are constructed from the measurement of incremental parameters, and thus reproduce transconductance and output conductance accurately, making the model superior for analog circuit design. The approach demonstrates a 2-3* improvement in total simulation time of a ring oscillator over the BSIM model in SPICE. The model affords a global accuracy of 4% in the L/sub D/-V/sub DS/ characteristics of 1- mu m enhancement and depletion MOSFETs. >

Spice Model for Transient Analysis of EEPROM Cells

Abstract: An equivalent model for the EEPROAM cell, described on a SPICE circuit analyzer. is used for the transient analysis of erase(E)/write(W) characteristics with ramp waveform programming pulses. The results of the simulation are compared with the experiemental data obtained by an innovative method for measuring E/W curves. The validation of the model is made over different variations of the cell lay-out, different programming voltages and diffrernt rise times for the ramp of the programming pulse.

A charge-conserving non-quasistatic MOSFET model for SPICE transient analysis

Abstract: An analytic charge-conserving nonquasistatic (NQS) model has been derived for long-channel MOSFETs and implemented in SPICE3. It is based on an approximate solution to the current-continuity equation. Comparison has been made among this model, the numerical solution to the 1-D current-continuity equation, and the quasistatic (QS) SPICE models. The charge injection at the turnoff transient of a NMOS switch has been simulated using this model and conventional QS models, and it has been found that the QS models give inaccurate results even for the moderately short channel (3- mu m) MOSFETs when the input voltage is changing at the moment of turnoff. A differential sample-hold circuit has also been simulated using this model, and the results are compared with those from QS models. The CPU time using this model is around 3 to 4 times longer than for the conventional QS SPICE models. >

Power MOS FET Models for ``Switching'' Circuits

Abstract: A compact model of the Power VDMOS Transistor compatible with the circuit simulator `` SPICE2'' is described in this article. This model is applied to the simulation of switching circuit with resistive and inductive loads; comparisons with experimental results are presented.

Analytical model of GaAs MESFET output conductance

Abstract: An analytical model of GaAs MESFET output conductance with frequency- and temperature-dependent parameters has been developed. The accuracy of the model was tested by comparing the simulated results with actual data of devices with low pinch-off voltage. The results showed considerable improvement when compared with the simple Curtice model. It is concluded that since the simple analytical expressions are easily incorporated into standard MESFET circuit simulation programs such as SPICE, this model helps to overcome a major impediment to the design of precision GaAs analog and digital ICs. >

Generation of transconductance grounded capacitor filters by signal-flow graph simulation of LC-ladders

Abstract: The methods are presented for generating active simulations of LC-ladders, based on signal-flow graphs. Both methods use only tunable transconductance elements and grounded capacitors. Furthermore, all transconductances except possibly one are identical and all capacitors are grounded, making the approach extremely convenient for integration with automated systematic design procedures and dense layout. SPICE simulations of the circuits with actual CMOS transconductance have been used to verify the performance. >

A high-resolution CMOS comparator

Abstract: A new high-speed high-resolution CMOS comparator is reported in this paper. A new offset-voltage-cancellation technique is used to reduce the effect of clock feed-through or charge pumping. The effective input voltage is doubled by the use of a cross-multiplexed technique. SPICE simulations using a modified MOS3 model (Wong 1986) show that the comparator reported here is capable of resolving 40 μV in less than 2·5 μs and 100μV in 1 μs.

A canonical continuous-time MOSFET-capacitor filter with high linearity

Abstract: The authors propose a synthesis of fully integrated canonical continuous-time filters with a high degree of linearity. The synthesis method is based on a differential current-integrator with a simple capacitor. A method to reduce the number of MOS transistors has also been presented. A third-order leapfrog filter is realized by the proposed method as an example. A total harmonic distortion less than 0.03% is obtained by SPICE analysis. The proposed method is advantageous, especially in the realization of higher-order filters, because of the reduction of higher-order filters, because of the reduction in chip area and manufacturing cost. >

Modeling of crosstalk in coupled microstrip lines

Abstract: A computer simulation of the crosstalk between coupled microstrip lines in both the time and frequency domains is presented. A SPICE software package is used to include inductive and capacitive coupling effects. The crosstalk results for various line parameters and line terminations are compared with results published in the literature. A technique for correlating the time- and frequency-domain crosstalk is presented. >