Showing papers on "Spice published in 1990"
TL;DR: In this article, a SPICE model for modeling GaAs MESFET devices more accurately is discussed, in particular small-signal parameters are accurately modeled over a wide range of bias conditions.
Abstract: A SPICE model for modeling GaAs MESFET devices more accurately is discussed. In particular, small-signal parameters are accurately modeled over a wide range of bias conditions. These results were achieved by modifying the model equations of H. Statz et al. (see IEEE Trans. Electron. Devices, vol.3, no.2, p.160-9, 1987) to better represent the variation of I/sub ds/ as a function of the applied voltage. The model applies over a large range of pinch-off voltages, allows size scaling of devices, and is suited for modeling R/sub ds/ changes with frequency. The Statz equations are used to represent diode characteristics and capacitive components of the model. >
155 citations
TL;DR: In this article, a linearity study of the propagation delay of bipolar circuits carried out using a SPICE program is discussed, and therefore analytical propagation delay expressions for ECL and CML circuits are derived using a sensitivity analysis.
Abstract: A linearity study of the propagation delay of bipolar circuits carried out using a SPICE program is discussed. It is found that the behavior of the propagation delay is quite linear, and therefore analytical propagation delay expressions for ECL and CML circuits are derived using a sensitivity analysis. The validity of the expressions is checked by SPICE simulations and comparison to experimental data published in the literature, and agreement is within 5%. The expressions indicate that there is an optimum value of load resistance for logic circuits in order to achieve a minimum propagation delay. For present technology, logic circuits for silicon transistors can operate at the current density corresponding to maximum f/sub T/, and logic circuits for AlGaAs-GaAs heterojunction bipolar transistors (HBTs) should operate at a current density lower than that of maximum f/sub T/. Therefore, it is important to increase the collector current density of maximum f/sub T/ for silicon bipolar circuits, or to decrease the base resistance R/sub B/ and the forward transit time tau /sub F/ for HBT circuits, in order to increase the circuit speed. >
94 citations
TL;DR: In this paper, a pn-diode micro-model representing forward and reverse recovery phenomena for power electronic simulation, especially simulations using SPICE2, was proposed to compensate the incompleteness of the diode model in current circuit simulation packages.
Abstract: A pn-diode micro-model representing forward and reverse recovery phenomena for power electronic simulation, especially simulations using SPICE2 is presented. The model is proposed to compensate the incompleteness of the diode model in current circuit simulation packages. In the forward recovery submodel, the diode bulk resistance modulation and its forward current dependence are included. In the reverse recovery submodel, the charge control equation for excess storage carriers is employed to simulate the detailed behavior. A procedure is described for extracting the model's physical parameters from data sheet information. The model is verified by a comparison of experimental results for several different tests with SPICE simulations. A discussion is given of extending the applicability of the micro-model to the simulation of p-i-n diode behaviour. >
94 citations
Book•
01 Jan 1990
TL;DR: This volume provides a time-and-effort-saving introduction to the PSpice simulator as a requisite for moving to SPICE.
Abstract: Computer-aided analysis and design is fast becoming a required skill for today's electronic engineers/technicians. SPICE is often the tool of choice. However because it runs on a mainframe or VAX-class computer, it must usually be learned at the PC level using the PSpice simulator. This volume provides a time-and-effort-saving introduction to the PSpice simulator as a requisite for moving to SPICE. The author introduces SPICE simulation; considers DC and AC circuits; outlines semiconductor devices modelling; explores digital logic circuits; and considers difficulties.
79 citations
TL;DR: In this paper, a charge-based model for vertical DMOSTs is developed and implemented in SPICE, which is derived from regional quasi-static analyses of carrier transport which implicitly characterize the device currents and charges and which require numerical solution Newton-Raphson iterative device solutions.
Abstract: A physical, seminumerical charge-based model for vertical DMOSTs is developed and implemented in SPICE The model is derived from regional quasi-static analyses of carrier transport which implicitly characterize the device currents and charges and which require numerical solution Newton-Raphson iterative device solutions are derived within the circuit nodal analysis framework of SPICE PISCES simulations and measurements of test devices support the model, which is demonstrated in DC and transient SPICE simulations of VDMOSTs and high-voltage integrated circuits (HVICs) >
66 citations
06 Feb 1990
TL;DR: The electrothermal simulator (ETS) as mentioned in this paper is based on the alternating operation of an electrical and thermal analysis program, which is used for integrated circuits to simulate the thermal properties of integrated circuits.
Abstract: The electrothermal simulator (ETS) for integrated circuits is presented. It is based on the alternating operation of an electrical and thermal analysis program. The main links between these two simulators are the model cards, as in a normal simulation program with IC emphasis (SPICE) input, but now provided for each circuit component separately. All temperature-dependent parameters are updated between iterations. A static example simulated with ETS shows the importance of such a combined electrothermal simulation. Future developments are also indicated. >
40 citations
LEMO1
TL;DR: In this paper, an accurate equivalent network for modelling the skin effect is presented, which is applicable regardless of the geometry of the microstrip line, especially when the thickness is greater than the width.
Abstract: An accurate equivalent network for modelling the skin-effect is presented. No specific approximation in the frequency behaviour is used. The method is therefore applicable whatever the geometry of the microstrip line, especially when the thickness is greater than the width. The frequency-dependent parameters of a transmission microstrip line as well as the attenuation are simulated using SPICE. Very good agreement is obtained with other published results.
38 citations
TL;DR: A simple general expression for the gate voltage dependence of the effective electron mobility is derived for use in SPICE circuit simulation, which is quite accurate over a wide range of channel doping concentrations and gate oxide thicknesses, without the need for fitting parameters.
Abstract: From the physical insights provided by the universal effective mobility versus effective vertical electric field curve for electrons in MOS inversion layers, a simple general expression for the gate voltage dependence of the effective electron mobility is derived for use in SPICE circuit simulation. This expression is quite accurate over a wide range of channel doping concentrations and gate oxide thicknesses, without the need for fitting parameters, such as the theta parameter of the current SPICE level 3 mobility degradation model. It is, therefore, a much more universal model than the present SPICE level 3 mobility expression. Furthermore, the relative accuracy of this new model compared to the current SPICE model is expected to increase at the higher vertical electric fields typical of submicrometer oxide semiconductor field effect transistors (MOSFETs). >
29 citations
TL;DR: Using the SPICE circuit analysis computer program to simulate a lossless multiconductor transmission line is investigated in this article, where it is demonstrated that for the case of a homogeneous dielectric, the multiconductor line can be represented by a system of standard two-wire lines which is not based on modal decomposition.
Abstract: Using the SPICE circuit analysis computer program to simulate a lossless multiconductor transmission line is investigated. It is demonstrated that for the case of a homogeneous dielectric, the multiconductor line can be represented by a system of standard two-wire lines which is not based on modal decomposition. This system is readily modeled with SPICE. While restricted to situations where the dielectric constant can be assumed uniform, the present method has the advantage of an intuitive relationship to the conductor configuration, simpler SPICE input data requirements, and an improvement in computer run time over other methods. >
25 citations
05 Mar 1990
TL;DR: In this article, an enhanced SPICE MOSFET circuit simulator model is presented and shown to be very effective in simulating device characteristics such as output conductance and transconductance.
Abstract: An enhanced SPICE MOSFET circuit simulator model is presented and shown to be very effective in simulating device characteristics. During formulation of the model, special attention was given to its ability to accurately simulate device output conductance and transconductance; thus the emphasis was on ensuring the model's suitability for analog as well as digital purposes. Parameter extract procedures using both directed nonlinear least-squares strategies and direct extraction methods with straightforward analytical equation solving were developed for the model. These procedures are described, and the accuracy and suitability of the direct methods are assessed. Comparisons between the results obtained using these methods and the more general parameter optimization schemes demonstrate that the direct parameter extraction procedure can be almost as accurate as the optimization methods providing the data used are chosen carefully. >
21 citations
01 May 1990
TL;DR: In this paper, an approach to the design of linear transconductance elements with a very large linear input range is explored, and a specific circuit is simulated by SPICE as an example.
Abstract: Current addition, an approach to the design of linear transconductance elements with a very large linear input range, is explored. Design tradeoffs are discussed and a specific circuit is simulated by SPICE as an example. The results show that for a power supply of +or-5 V, the nonlinearity error of the sample circuit is controlled to +or-0.3% over a +or-3-V input range. OTA (operational transconductance amplifier) parameters such as tuning capability, frequency response, and output impedance are examined. The body effect is considered. A second-order filter is presented as an application. >
TL;DR: A non-ideal SCR macromodel for analog power circuit simulation using SPICE has been developed in this article, which adds important second-order effects such as overvoltage and critical dV/sub Ak//dt switch-on, turnon, and tq times, threshold gate trigger voltage, and nonlinear on-state characteristics.
Abstract: A nonideal SCR (silicon controlled rectifier) macromodel for analog power circuit simulation using SPICE has been developed. This model adds important second-order effects such as overvoltage and critical dV/sub Ak//dt switch-on, turn-on, and tq times, threshold gate trigger voltage, and nonlinear on-state characteristics. The parameters of any specific SCR can be easily obtained from its data sheet specifications. Any kind of thyristor, from high power up to fast turn-off, can be modeled with only 10 well-defined parameters. Electronic systems with electrical transients can be successfully simulated. Good agreement between manufacturer data sheet specifications and simulated results has been observed for all the thyristors considered. >
01 Apr 1990
TL;DR: A SPICE compatible macromodel has been devised for the simulation of 'current feedback' type operational amplifiers, the major advantage of this type of amplifier is high speed and the emphasis is on the accurate prediction of AC characteristics.
Abstract: A SPICE compatible macromodel has been devised for the simulation of 'current feedback' type operational amplifiers. Since the major advantage of this type of amplifier is high speed, the emphasis is on the accurate prediction of AC characteristics. A practical example is given, together with a comparison of measured and simulated performance. >
TL;DR: In this article, the degradation of bipolar transistors at 300 and 110 K under DC base-emitter reverse bias stress is discussed, and a method for modeling the degradation due to the stress from a periodic signal is proposed.
Abstract: The degradation of bipolar transistors at 300 and 110 K under DC base-emitter reverse-bias stress is discussed. It is found that, for the same reverse voltage, the reverse current is about three to four times smaller at 100 than at 300 K, but the rate of base current degradation is several times larger. A method for modeling the degradation due to the stress from a periodic signal is proposed. The resulting expression for degradation is compatible with the SPICE bipolar model and has been used to simulate the degradation of a BiCMOS inverter operating at 300 and 110 K. >
Patent•
25 Jun 1990
TL;DR: In this article, a preprocessor automatically assigns one of the models in the SPICE deck for modeling a particular device in a circuit simulated by the simulator, based on device size, whether it is connected to power supply or ground and device type.
Abstract: A method for generating input data for a SPICE simulator in which a preprocessor computer program automatically assigns one of the models in the SPICE deck for modeling a particular device in a circuit simulated by the SPICE deck. Data which specifies valid device size ranges for a particular model is added to the SPICE deck prior to preprocessing. The model is assigned by the preprocessor computer program based upon device size, whether it is connected to power supply or ground and device type (P or N). The preprocessor output data is in a format usable by a commercially available SPICE program.
09 Dec 1990
TL;DR: In this article, a model for bipolar hot-carrier degradation has been implemented into the BERT circuit reliability simulator, thus allowing both bipolar and BiCMOS circuit degradation to be simulated.
Abstract: A model for bipolar hot-carrier degradation has been implemented into the BERT circuit reliability simulator, thus allowing both bipolar and BiCMOS circuit degradation to be simulated The bipolar module consists of a preprocessor and post-processor for SPICE that require no modification to the SPICE code Experimental results indicate that the degradation due to alternating reverse-forward stressing representative of BiCMOS gate operation agrees with the Delta I/sub B/ model from DC measurements The base current degradation for a single device due to electrostatic discharge stress and the offset voltage degradation for an emitter-coupled pair due to DC stress are accurately predicted by the simulator >
TL;DR: In this paper, an ISFET model suitable for direct applications as a built-in model in SPICE is presented, which is formulated by modifying the MOST threshold voltage, which, for the IsFET, is chemically influenced by ionic interaction between the electrolyte and the insulator.
Abstract: An ISFET model suitable for direct applications as a built-in model in SPICE, is presented. The ISFET 'static' model equations are formulated by modifying the MOST threshold voltage which, for the ISFET, is chemically influenced by ionic interaction between the electrolyte and the insulator. The ISFET 'large-signal model' has been obtained from the site-binding model of the insulator-electrolyte interface, combined with the Gouy-Chapman-Stern theory of the electrical double layer at this interface, varying the Meyer's large-signal model of the MOST in SPICE. The proposed model leads to the introduction of twelve new parameters that the user of SPICE can specify in the MODEL card. For these parameters the temperature dependence has also been implemented. The model has been used to simulate the output characteristics of Ag/AgCl KCl SiO2 Si and Ag/AgCl NaCl Al2O3 SiO2 Si ISFET structures at different pH values, and ISFET-based circuits, obtaining a good agreement with experimentally measured values.
TL;DR: In this article, a design technique for MESFET mixers is described based on a mixer analysis program (MIXAN) designed to obtain the value of conversion gain and evaluate the influence of the embedding impedances for any local oscillator power and DC bias, in order to optimized the mixer performance.
Abstract: A design technique for MESFET mixers is described. This technique is based on a mixer analysis program (MIXAN) designed to obtain the value of conversion gain and evaluate the influence of the embedding impedances for any local oscillator power and DC bias, in order to optimized the mixer performance. The MIXAN program, which uses SPICE as a subroutine to determine large-signal current and voltage waveforms, is able to obtain the operating conditions for maximum conversion gain. The good agreement between experimental and simulation results for X-band drain and gate mixers proves the validity of the design technique. >
TL;DR: In this paper, a topology-independent method is proposed for simulating the responses of open and closed-loop quasiresonant DC-DC convertors operating in the zero-current-switching mode (ZCS-QRC).
Abstract: A simple, topology-independent method is proposed for simulating the responses of open and closed-loop quasiresonant DC-DC convertors operating in the zero-current-switching mode (ZCS-QRC). The method hinges on the substitution of the resonant network and switch assembly, fundamental in the realisation of such systems, by an equivalent circuit which represents its average behaviour. This permits simulation by a general-purpose electronic circuit simulator such as SPICE. The proposed approach is demonstrated by presenting the simulation results of a buck-boost convertor.
05 Mar 1990
TL;DR: In this paper, a fast and cost-efficient system to measure level-3 SPICE parameters is described, which takes 30 measurements in 18 measurement cycles using six MOSFETs and an oxide capacitor.
Abstract: A fast and cost-efficient system to measure level-3 SPICE parameters is described. The extraction process takes 30 measurements in 18 measurement cycles using six MOSFETs and an oxide capacitor. Many of the measurements are performed in parallel and this significantly reduces the combined measurement and extraction time. >
17 Sep 1990
TL;DR: In this paper, the authors reviewed the evolution of SPICE from the initial research project at the University of California at Berkeley in the late 1960s, through the 1970s and 1980s, and into the 1990s.
Abstract: The author reviews the evolution of SPICE from the initial research project at the University of California at Berkeley in the late 1960s, through the 1970s and 1980s, and into the 1990s. A general description of the SPICE techniques, analysis modes, and intended areas of application is provided. The relation between solution algorithms, semiconductor device models, and circuits to be characterized is explored in order to clarify the merits and limits of this program. The current trends in electrical circuit simulation and the role of SPICE in its third decade are then presented. It is concluded that the developments in circuit simulation do not make SPICE obsolete, but rather complement it. SPICE will continue to be the main electrical simulator because it solves the fundamental equations of an electrical system. >
16 Dec 1990
TL;DR: The stability analyses of the CNN-circuit has been carried out in the case when the sigmoid has offset, nonconstant saturation level and nonlinearity, and the effect of the internal parasitic poles on the circuit performance has been studied through several simulations.
Abstract: The stability analyses of the CNN-circuit has been carried out in the case when the sigmoid has offset, nonconstant saturation level and nonlinearity. Also the effect of the internal parasitic poles on the circuit performance has been studied through several simulations. The analyses have been verified with the SPICE simulations done on the experimental 4-by-4 CNN circuit. >
TL;DR: In this article, the authors proposed a simplified method for the construction of time-domain solutions by the superposition of modes, which requires that the logic-gate terminal impedances be approximated by linear effective resistances that can be adequately determined by SPICE analysis of actual logic gates.
Abstract: The construction of time-domain solutions by the superposition of modes is explained for the general case, which may not have any symmetry in the lines or terminations. This simplified method requires that the logic-gate terminal impedances be approximated by linear effective resistances that can be adequately determined by SPICE analysis of the actual logic gates. Several examples of results of crosstalk calculations made by the simplified method are presented and compared with corresponding results obtained using the SPICE transmission-line methods of Tripathi and Rettig (IEEE Trans. Microwave Theory Tech., vol. MTT-33, no.12, p.1513-18, 1985) along with full SPICE models of the logic gates. The simplified approach is shown to give satisfactory agreement for most purposes. >
07 Oct 1990
TL;DR: In this paper, Monte Carlo DC SPICE simulation is used to assess the effect of the FET parameter spread on the functional yield of a chip, and it is found that the important factors for obtaining a high functional yield are strict control of FET characteristics and the stability and uniformity of the supply voltage on the chip.
Abstract: GaAs MESFET LSI design using E/D-DCFL (enhancement/depletion-directly coupled FET logic) circuits is considered. Monte Carlo DC SPICE simulation is used to assess the effect of the FET parameter spread on the functional yield of a chip. It is found that the important factors for obtaining a high functional yield are strict control of the FET characteristics and the stability and uniformity of the supply voltage on the chip. The functional yield model, including the supply voltage drop, agrees well with the results obtained in experiments on a 5 K gate array IC fabricated with 0.8- mu m-gate BP-MESFETs. >
01 May 1990
TL;DR: In this article, an analytical delay model for BiCMOS driver circuits is presented, which is based on physical device parameters and can be used to estimate both the pull-up and the pulldown times for a variety of circuit configurations.
Abstract: An analytical delay model for BiCMOS driver circuits which is based on physical device parameters and can be used to estimate both the pull-up and the pull-down times for a variety of circuit configurations is presented. The intrinsic delay associated with the bipolar transistors is taken into consideration by a charge control model that incorporates the high-injection effects upon the current gain and the base transport factor. Separate sets of delay equations are derived for the pull-up and pull-down transient responses because significant differences are shown to exist between the two cases. A comparison with SPICE circuit simulation results shows that the model predicts the respective delay times with less than 10% error in most cases. The influence of device dimensions upon the inverter delay time is investigated. It is demonstrated than an optimal area allocation exists between the CMOS and bipolar parts of the driver circuit when the total available area is limited, such as in standard cell configurations. >
13 May 1990
TL;DR: A strobed multiplier circuit for use in integrated neural network architectures that performs the two-quadrant weighting of interconnect signals via exponential charge packets onto capacitive summing buses is presented.
Abstract: A strobed multiplier circuit for use in integrated neural network architectures is presented. The circuit, which can be fabricated in a standard CMOS analog process, performs the two-quadrant weighting of interconnect signals via exponential charge packets onto capacitive summing buses. SPICE simulations and MOSIS fabrication results are presented. The proposed design is simple in structure, uses no operational amplifiers for the actual multiplication function, uses no power in the static mode, and has been implemented in standard 2 mu m analog CMOS processing. >
12 Aug 1990
TL;DR: In this paper, a dual-gate JFET model is presented based on the physical three-half power current-voltage relationship, which has the capability of independent biasing of top-gate and bottom-gate.
Abstract: A physical dual-gate JFET model is presented. The model is based on the physical three-half power current-voltage relationship. This model has the capability of independent biasing of top-gate and bottom-gate. Short channel velocity-saturation and an improved channel-length modulation model are also included. The model has been developed as a subroutine extension in SPICE. Self-consistent parameter extraction routines, based on an exact operational definition of each model parameter, have been developed in conjunction with the model. Unique extraction algorithms are developed for each model form. Only after consistent extraction routines are developed for the model within a circuit simulator are they applied to the physical device. This provides an exact operational definition for each model parameter. >
12 Mar 1990
TL;DR: The presented macromodels can be incorporated into the CAD tool MOGLO for automatic transistor sizing in CMOS logic circuits at low computational cost taking into account conflicting criteria such as delay, area and power.
Abstract: Accurate macromodels for CMOS transmission gates are presented. Signal delay, area consumption and power dissipation are determined by a few technology dependent parameters. Different transistor widths, input waveforms and varying loading conditions are considered. The calculated delay times of CMOS circuits including transmission gates differ only 10 percent when compared with SPICE results. The presented macromodels can be incorporated into the CAD tool MOGLO for automatic transistor sizing in CMOS logic circuits. MOGLO determines optimal tradeoff solutions for CMOS circuitry at low computational cost taking into account conflicting criteria such as delay, area and power. >
15 Oct 1990
TL;DR: In this paper, a SPICE gate turn-off thyristor (GTO) model is presented which simulates both the static negative differential resistance (NDR) I-V characteristics and the dynamic switching characteristics.
Abstract: The authors present a SPICE gate turn-off thyristor (GTO) model which simulates both the static negative differential resistance characteristics and the dynamic switching characteristics. The model consists of a parallel connection of two-transistors, three-resistor (2T-3R) cells. The accuracy of the model depends on the number of 2T-3R cells used. This multi-cell GTO model enables one to simulate the static-type negative differential resistance (NDR) I-V characteristics and the switching characteristics of the GTO with a high degree of accuracy. The experimental validation test shows that two parallel 2T-3R cells simulate the switching characteristics of the GTO accurately. A sensitivity study of the SPICE model performance with respect to the model parameters is used to develop the model synthesis procedure. >