Showing papers on "Spice published in 2004"

Transistor sizing for radiation hardening

Abstract: This paper presents an efficient and accurate numerical analysis technique to simulate single event upsets (SEUs) in logic circuits. Experimental results that show the method is accurate to within 10% of the results obtained using SPICE are provided. The proposed method is used to study the ability of a CMOS gate to tolerate SEUs as a function of injected charge and transistor sizing (aspect ratio W/L). A novel radiation hardening technique to calculate the minimum transistor size required to make a CMOS gate immune to SEUs is also presented. The results agree well with SPICE simulations, while allowing for very fast analysis. The technique can be easily integrated into design automation tools to harden sensitive portions of logic circuits.

A closed loop transcutaneous power transfer system for implantable devices with enhanced stability

Abstract: This paper describes a closed-loop wireless inductive power transfer system for an implantable retinal prosthetic device. The proposed system is designed to ensure optimal power transfer to the implanted unit despite coil displacements and changes in load current while minimizing the sensitivity to component and process variation. Based on the system modeling, stability constraints are identified and applied to the feedback control system. The model is crucial in determining component values, circuit topology and number of transmitted bits per sampling period required to ensure system stability. In addition, the model significantly reduces design iterations compounded by lengthy circuit simulation. The model is verified by Matlab and SPICE level simulations. The critical analog circuits of the control system have been designed and fabricated through AMI 1.6 /spl mu/m process.

Spice equivalent circuit of a two-parallel-wires shielded cable for evaluation of the RF induced Voltages at the terminations

Abstract: A SPICE circuit model is developed for the evaluation in frequency and time domain, of the common and differential mode voltages at the terminals of a two-parallel-wires shielded cable during a current injection test. The proposed circuit is an exact equivalent of the model's governing multiconductor transmission line equations without the need of any subdivision in elementary cells and takes into account the presence of both transfer impedance and admittance.

New current-mode special function continuous-time active filters employing only OTAs and OPAMPs

Abstract: This paper reports three current mode second order filters, each of which realizes a specific function without any external passive elements. These filters realize low-pass notch (LPN), high-pass notch (HPN) and all-pass (AP) functions. Two OPAMPs, a double output OTA and a single output OTA are employed for each circuit. The filter structures can be easily cascaded since they have high output impedances. This property is especially useful for achieving high-order filters using these LPN and HPN filters as building blocks. The presented theory is verified with macro models in SPICE simulations and, using the SPICE parameters of the layout technology, post layout simulations are carried out, with parasitics extracted from the layouts of the filter chips.

Investigation of Compact Models for RF Noise in

Abstract: A comprehensive investigation of the SPICE and unified compact noise models is performed by comparison with the more fundamental hierarchical hydrodynamic device model. It is shown that the rather simple SPICE and unified compact noise models yield good results for frequencies up to 10 GHz for state-of-the-art SiGe HBTs with a low base resistance. The base noise resistance, a key parameter of the compact noise models turns out to be independent of frequency and bias. It can be well estimated based on the sheet resistance of the intrinsic and extrinsic base or with the modified circle-fit method. The unified model, which in comparison to the SPICE model considers in addition the finite transit time of shot noise, is found to be somewhat more accurate than the SPICE model, especially at higher frequencies and collector currents. But this is achieved at the expense of a transit time parameter which cannot be determined without accurate and detailed noise measurements or physics-based numerical simulations.

Investigation of compact models for RF noise in SiGe HBTs by hydrodynamic device simulation

Abstract: A comprehensive investigation of the SPICE and unified compact noise models is performed by comparison with the more fundamental hierarchical hydrodynamic device model. It is shown that the rather simple SPICE and unified compact noise models yield good results for frequencies up to 10 GHz for state-of-the-art SiGe HBTs with a low base resistance. The base noise resistance, a key parameter of the compact noise models turns out to be independent of frequency and bias. It can be well estimated based on the sheet resistance of the intrinsic and extrinsic base or with the modified circle-fit method. The unified model, which in comparison to the SPICE model considers in addition the finite transit time of shot noise, is found to be somewhat more accurate than the SPICE model, especially at higher frequencies and collector currents. But this is achieved at the expense of a transit time parameter which cannot be determined without accurate and detailed noise measurements or physics-based numerical simulations.

Automated extraction of broadly applicable nonlinear analog macromodels from SPICE-level descriptions

Abstract: Automated techniques for generating macromodels from SPICE-level circuit descriptions are rapidly gaining importance as a sustainable methodology for the design of large, complex mixed-signal SoCs and SiPs. We demonstrate the efficacy of a novel macromodel extraction technique, dubbed piecewise polynomial (PWP), for extracting broadly-applicable general-purpose macromodels from SPICE netlists. A key advantage of PWP over other methods is that it can generate a single macromodel that captures linear, weakly nonlinear and strongly non near system dynamics. We demonstrate the application of PWP using a current-mirror op-amp, comparing simulations of the macromodel against those of the original SPICE circuit using DC, AC, harmonic balance and transient analyses. We also illustrate how PWP-generated macromodels can be used for system-level simulation using a simple analog-digital converter example. We confirm excellent accuracies, relative to full SPICE circuit simulation, while achieving order-of-magnitude speedups.

A current controlled conveyor based proportional-integral-derivative (pid) controller

Abstract: A new PID controller realized with positive type, second generation current controlled conveyers (CCCII++) and passive components is presented. The outputs of SPICE simulations of the proposed circuit are verified with the theoretical expectations.

SPICE compatible equivalent circuit of the energy conversion processes in thermoelectric modules

Abstract: The objective of this work was to develop a SPICE compatible equivalent circuit of a thermoelectric module (TEM). A methodology is developed for extracting the parameters of the proposed model from manufacturers' data of thermoelectric coolers (TEC) and thermoelectric generators (TEG). The model could be helpful for analyzing the drive requirements of TEC and loading effects of TEG. The present model is compatible with PSPICE or other electric circuit simulators. An important feature of the model is its ability to generate small signal transfer functions that can be used to design feedback networks for temperature control applications.

Full-wave analysis in SPICE via model-order reduction

Abstract: Full-wave analysis is traditionally performed in the frequency domain, or in the time domain using specialized simulators (e.g., finite difference time domain). We describe here an approach that allows us to generate full-wave models for SPICE simulation. The advantage of this approach is that it allows us to easily consider the effects of arbitrary terminations. A frequency-domain finite-element method or method-of-moments solver is used to determine the frequency response of a three-dimensional structure, and then a SPICE model is constructed, which matches this frequency response across a specified frequency band. Some examples are presented to demonstrate the efficacy of the technique.

A charge-control SPICE engineering model for the parasitic bipolar transistor action in SOI CMOS single-event upsets

Abstract: An ion strike on an SOI CMOS transistor produces a charge cloud of electron-hole pairs. The subsequent behavior of the charge cloud as it spreads and impinges on the source and drain junctions is explained by 1-D analytical solutions and by 2-D device simulations. By examining the charge cloud from a "top view" perspective and a "side view" perspective, it is shown that a 2-D "side view" simulation gives about the same electrical behavior as would a 3-D simulation, thereby eliminating the necessity for expensive and time-consuming 3-D simulations. It is further shown that the electrical behavior predicted by 2-D simulations can be captured in a simple bipolar SPICE model, which is necessary for practical SEU analysis of large numbers of logic and memory cell types. The SPICE model is based on fundamental physical parameters, not curve-fitting. The predictions of the SPICE model correlate well with experimental SEU sensitivities of a D-type flip-flop and a six-transistor SRAM cell processed in a 0.35 /spl mu/m SOI technology.

History-effect-conscious SPICE model extraction for PD-SOI technology

Abstract: This work presents explicit fitting guidelines for AC and DC characteristics, specifically focused on accurate modeling of the history effects in the PD-SOI CMOS circuits. The body potential of the PD-SOI device is primarily determined by the diode current, gate-body current, impact ionization current, junction capacitance, and gate-body capacitance. This paper also discusses artifacts associated with the parasitic currents and highly-resistive thin-body of the PD-SOI.

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects

Abstract: Substrate noise is a major obstacle for mixed-signal integration. In this paper we propose a fast and accurate high-level methodology to simulate substrate noise generated by large digital circuits. The methodology can handle any substrate type, e.g. bulk-type or EPI-type, and takes into account the effects of interconnect and supply. For each standard cell a substrate macromodel is used in order to efficiently simulate the total system, which consists of a network of such macromodels. For a 40K gates telecom circuit fabricated in a 0.18 mm CMOS process, measurements indicate that substrate noise is simulated by using our methodology within 20% error but several orders of magnitude faster in CPU time than a full SPICE simulation..

Spice storage and dispensing spoon

Abstract: A spice storage and dispensing system is configured as a spoon and includes a handle for the storage of spice and a bowl for the measurement and dispensing of spice received from the handle.

Process-insensitive low-power design of switched-capacitor integrators

Abstract: A generalized analytical technique is developed to design power optimized switched-capacitor integrators taking process variations into account. It is shown that the performance of a robustly designed power optimum switched-capacitor integrator is a monotonic function of the slew rate and the transconductance of the amplifier. The framework provides an analytical solution for fabrication foundry independent analog design and therefore eliminates the need for Monte Carlo simulations to estimate the effect of the worst-case performance variations. With this analytical approach, it is possible to migrate the design to technologies with smaller feature sizes while obtaining monotonic improvement in the performance. The validity of the proposed analytical model for the design of robust switched-capacitor integrators is demonstrated through transistor-level SPICE simulations using BSIM3v3 models.

Simultaneous switching noise in IBIS models

Abstract: In this paper, a tool to convert SPICE netlists to IBIS (Input/Output Buffer Information Specification) models is presented This tool simulates the netlist on a user-desirable SPICE engine and produces both static and dynamic characteristics of the IBIS model. A CMOS driver circuit is simulated in HSPICE and compared with an equivalent circuit created with IBIS models of the same drivers. Outputs from the drivers are compared IBIS models are also compared against macro-models of nonlinear digital drivers using spline functions with finite time difference approximation modeling techniques.

Modeling and behavioral SPICE simulation of a self adjusting current-fed push-pull parallel resonant inverter (SA-CFPPRI)

Abstract: A modeling methodology that can be applied to power systems that include nonlinearities and phase lock loops was developed and used to model and investigate the properties of a self adjusting current-fed push-pull parallel resonant inverter (SA-CFPPRI). This topology is based on the push-pull parallel resonant inverter in which a controlled variable inductor is incorporated to keep the system at resonant frequency over a given frequency range and under a nonconstant reactive load. The analytical expression and SPICE models developed in this study were found to be in good agreement with experimental results. PSPICE/ORCAD (Cadence, USA) files (Evaluation version 9.2) of the system under study are available for download from http://www.ee.bgu.ac.il//spl sim/pel/download.htm.

A Ferroelectric Capacitor Mathematical Model for Spice Simulation

Abstract: A behavioral ferroelectric capacitor model based on Q-V expression with model parameters extracted from experimental hysteresis loops is proposed. A compact equivalent circuit of this model is described for spice simulation of nonvolatile memories. Excellent agreement was achieved between our measurements and simulation results. The runtime for simulation of a hysteresis loop with 10,000 points is 1.55 seconds, which is similar to 1.15 seconds for a normal capacitor.

Application Note 7534 A New PSPICE Electro-Thermal Subcircuit For Power MOSFETs

Abstract: An empirical self-heating SPICE MOSFET model which accurately portrays the vertical DMOS power MOSFET electrical and thermal responses is presented. This macro-model implementation is the culmination of years of evolution in MOSFET modeling. This new version brings together the thermal and the electrical models of a VDMOS MOSFET. The existing electrical model [2,3] is highly accurate and is recognized in the industry. The sequence of the model calibration procedure using parametric data is described. Simulation response of the new self-heating MOSFET model track the dynamic thermal response and is independent of SPICE’s global temperature definition.

SPICE model of AlGaN/GaN HEMTs and simulation of VCO and power amplifier

Abstract: SPICE model parameters are extracted from reported experimental data. The model is implemented in the Cadence Affirma Analog Circuit Design Environment and Spectre simulator is used to simulate class-E power amplifier and ring voltage controlled oscillator (VCO) circuits. The availability of the SPICE model for GaN HEMTs ensures optimization of analog/RF circuits before an expensive cut-and-try method is employed.

SPICE compatible circuit models for partial reluctance K

Abstract: We are the fist to develop SPICE compatible circuit model for partial reluctance K. It can be combined with any partial reluctance based extraction method to perform FiLC simulation directly without the need of inverting partial reluctance matrix back into partial inductance domain or modifying conventional simulator. To build symmetrical partial reluctance matrix, we also prw posed blocked K method based on group concept to cover more magnetic couplings. Both quantitive analysis and experiments demonstrated that the combination of the SPICE compatible circuit model and the blocked K method has the best compromise between accuracy and performance among all SPICE compatible sparsificatioo techniques.

SPICE macro models for annular MOSFETs

Abstract: MOSFETs with annular, or enclosed, geometries are now finding frequent use in rad-hard by design (RHBD) approaches to designing custom CMOS ASICs for aerospace applications. Unfortunately, these devices are not accurately modeled by the BSIM3 models normally provided for devices with ordinary rectangular gates. We present a SPICE macro model for an annular n-channel MOSFET to account for the annular geometry effects on gate overlap capacitance and output conductance.

The Spice Market Expands

Abstract: domestic production. According to the American Spice Trade Association (ASTA, 2001), U.S. consumption of spices exceeds 1 billion lb/year. Of that quantity, approximately two-thirds is imported. In addition, U.S. per capita consumption continued to grow from 2.1 lb in 1980 to approximately 3.6 lb in 2000. According to the International Trade Centre of the United Nations Conference on Trade and Development/World Trade Organization (UNCTAD/WTO, 2002), the world market for imported spices and culinary herbs is large, valued at just over $2.3 billion, with India accounting for 30% of exports. Annual worldwide imports grew at an average 8.5% a year, indicating that consumption of spices continues to grow. Fig. 1 shows some typical tropical spices. Table 1 illustrates some of the most important tropical spices and their main producing countries. And Table 2 illustrates the value and tonnage of U.S. spice imports by product for 2002. While the average consumer uses the term spices for the most part to refer to the traditional ones such as black pepper, cinnamon, and cloves, the spice trade generally uses four categories to further define the term: tropical aromatics or spices; herbs; spice seeds or seeds; and dehydrated vegetables. ASTA defines spices as “any dried plant product used primarily for seasoning purposes.” Included are tropical aromatics, more commonly referred to in the trade as “spices” (pepper, cinnamon, cloves, etc.), herbs (basil, oregano, marjoram, etc.), spice seeds (sesame, poppy, mustard, etc.), and dehydrated vegetables (onions, garlic, etc.). The definitions can be found at www.astaspice. org/spice/ frame_spice.htm, under “Spice Definitions and Glossary.” The Food and Drug Administration defines spices similarly, except that dehySpices and Ethnic Foods

Effective digital IO pin modeling methodology based on IBIS model

Abstract: IBIS (I/O buffer information specification) model is widely used in signal integrity analysis of on-board high-speed digital systems. IBIS model is converted equivalent SPICE behavioral model when used board-level simulations. It is important to represent accurately output buffer's switching characteristics converting IBIS model to SPICE behavioral model. This paper proposes a new modeling algorithm to represent output buffer's switching characteristics in IBIS model. The accuracy of the proposed algorithm has verified through SPICE simulation with other behavioral models.

A novel SPICE macromodel of BJTs including the temperature dependence of high-injection effects

Abstract: In this work a novel steady-state ABM-based BJT macromodel is presented, which can be successfully adopted for accurately describing the electrothermal behavior of devices consisting of several elementary transistors connected in parallel. As an enhancement with respect to other approaches, the temperature dependence of the onset of high-injection effects is taken into account, which implies a complete description of possible electrothermal stabilizing mechanisms at high-current regimes.

Analysis techniques for obtaining the steady-state solution of MOS LC oscillators

Abstract: Accurate analysis techniques for estimating the periodic steady-state solution of MOS LC oscillators using short-channel device equations are presented. These techniques allow us to make quantitative estimates of the oscillator steady-state performance without the need for time-consuming transient simulations using simulators such as SPICE. Further, our engineering techniques provide insight and quantitative understanding on the design of current-day, deep-submicron MOS LC oscillators and serve as a starting point in a design methodology that includes complete phase noise/timing jitter analysis and optimization. Our analytical results for a cross-coupled LC oscillator that was previously fabricated and tested are in good agreement with SPICE simulations.

SET-based nano-circuit simulation and design method using HSPICE

Abstract: This paper presents a simulation and design method for complementary SET-based nano-circuits. A HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth-Death Markov chain is demonstrated and verified with Coulomb characteristics. It shows a reduced CPU time and more compatibility with other SPICE softwares on both Windows and Unix. The design methodology illustrates how to build CMOS-like SET circuits, and based on it, conventional static CMOS circuit design methodologies are all applicable to SET circuit designs. Simulation results show that, for 1M$\Omega$ junction resistance, the power consumption of a SET NAND2 gate is less than 0.3pW, and the propagation delay for a SET XOR2 gate is only 29.8ns while driving a 10aF load.

An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs

Abstract: This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate is derived, and a representation of digital switching noise in time domain can be easily calculated through a dedicated computer program. This representation is used to perform an analog simulation using SPICE, to evaluate the propagation of the switching noise through the parasitic elements of the package and of the bonding wires. Simulation results for two case studies are presented.

CMOS image sensor 3T Nwell photodiode pixel SPICE model

Abstract: CMOS image sensor pixel design requires accurate SPICE modeling to determine pixel performance. In this work, a standard Nwell/Psub photodiode with a 3 transistor pixel has been modeled using Cadence SPECTRE SPICE simulator fabricated using a conventional 0.18 /spl mu/m CMOS process technology. Pixel parameters such as voltage swing, clock feedthrough and pixel capacitance have been modeled using silicon based measurements of individual components. These components include reset source region, Nwell photodiode and source follower gate capacitances. In addition, nonlinear effects of the photodiode and source follower are included in the model. The accuracy of the model agrees well with measured pixel transient response.