Showing papers on "Spice published in 2008"

Switch-Mode Power Supplies Spice Simulations and Practical Designs

Abstract: Harness Powerful SPICE Simulation and Design Tools to Develop Cutting-Edge Switch-Mode Power Supplies Switch-Mode Power Supplies: SPICE Simulations and Practical Designs is a comprehensive resource on using SPICE as a power conversion design companion. This book uniquely bridges analysis and market reality to teach the development and marketing of state-of-the art switching converters. Invaluable to both the graduating student and the experienced design engineer, this guide explains how to derive founding equations of the most popular converters…design safe, reliable converters through numerous practical examples…and utilize SPICE simulations to virtually breadboard a converter on the PC before using the soldering iron. Filled with more than 600 illustrations, Switch-Mode Power Supplies: SPICE Simulations and Practical Designs enables you to: Derive founding equations of popular converters Understand and implement loop control via the book-exclusive small-signal models Design safe, reliable converters through practical examples Use SPICE simulations to virtually breadboard a converter on the PC Access design spreadsheets and simulation templates on the accompanying CD-ROM, with numerous examples running on OrCADE, ICAPSE, µCapE, TINAE, and more Inside This Powerful SPICE Simulation and Design Resource • Introduction to Power Conversion • Small-Signal Modeling • Feedback and Control Loops • Basic Blocks and Generic Models • Simulation and Design of Nonisolated Converters • Simulation and Design of Isolated Converters-Front-End Rectification and Power Factor Correction • Simulation and Design of Isolated Converters-The Flyback • Simulation and Design of Isolated Converters-The Forward Table of contents Foreword Preface Nomenclature Chapter 1. Introduction to Power Conversion Chapter 2. Small-Signal Modeling Chapter 3. Feedback and Control Loops Chapter 4. Basic Blocks and Generic Switched Models Chapter 5. Simulation and Designs of Nonisolated Converters Chapter 6. Simulations and Practical Designs of Off-Line Converters--The Front End Chapter 7. Simulations and Practical Designs of Flyback Converters Chapter 8. Simulations and Practical Designs of Forward Converters Conclusion Index

Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation

Abstract: The integration density of state-of-the-art electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by various design and manufacturing constraints, the integrated circuit reliability must be modeled and analyzed at the very beginning of design stages. This paper reviews some of the most important intrinsic wearout mechanisms of MOSFETs (including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability) and introduces new accelerated-lifetime and SPICE compact models of these wearout mechanisms. Based on these circuit-aging models, a new SPICE reliability simulation approach is proposed and demonstrated with a simplified SRAM design on a commercial 90-nm technology to help designers understand device-failure behaviors, predict circuit reliability, and improve product robustness.

SPICE model for lossy piezoelectric polymers

Abstract: This work presents the transmission line equivalent model for lossy piezoelectric polymers and its SPICE implementation. The model includes the mechanical/viscoelastic, dielectric/electrical, and piezoelectric/electromechanical losses in a novel way by using complex elastic, dielectric, and piezoelectric constants obtained from the measured impedances of PVDF and PVDF-TrFE samples by nonlinear regression technique. The equivalent circuit parameters are derived from analogies between a lossy electrical transmission line and acoustic wave propagation. The simulated impedance and phase plots of various samples, working in thickness mode, have been shown to agree well with the measured data.

A new full-wave rectifier circuit employing single dual-X current conveyor

Abstract: In this study, a novel voltage-mode full-wave rectifier with high-input impedance using a dual-X second-generation current conveyor and three enhancement-type n-channel metal-oxide semiconductor field-effect transistors (MOSFETs) is introduced. The proposed circuit does not employ any passive elements, and is simulated using SPICE program with level 49, 0.25 µm TSMC CMOS technology parameters to confirm the theory and exhibit the performance of the circuit.

Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects

Abstract: This paper deals in crosstalk analysis of a CMOS-gate-driven capacitively and inductively coupled interconnect. Alpha power-law model of a MOS transistor is used to represent a CMOS driver. This is combined with a transmission-line-based coupled-interconnect model to develop a composite driver-interconnect-load model for analytical purposes. On this basis, a transient analysis of crosstalk noise is carried out. Comparison of the analytical results with SPICE extracted results shows that the average error involved in estimating noise peak and their time of occurrence is less than 7%.

Neural-Based Models of Semiconductor Devices for SPICE Simulator

Abstract: The paper addresses a simple and fast new approach to implement Artificial Neural Networks (ANN) models for the MOS transistor into SPICE. The proposed approach involves two steps, the modeling phase of the device by NN providing its input/output patterns, and the SPICE implementation process of the resulting model. Using the Taylor series expansion, a neural based small-signal model is derived. The reliability of our approach is validated through simulations of some circuits in DC and small-signal analyses.

A Wideband Scalable and SPICE-Compatible Model for On-Chip Interconnects Up to 110 GHz

Abstract: A fully scalable and SPICE compatible wideband model of on-chip interconnects valid up to 110 GHz is presented in this paper. The series branches of the proposed multisegment model consist of an RL ladder network to capture the skin and proximity effects, as well as the substrate skin effect. Their values are obtained from a technique based on a modified effective loop inductance approach and complex image method. A CG network is used in the shunt branches of the model, which accounts for capacitive coupling through the oxide and substrate loss due to the electrical field, as well as the impact of dummy metal fills. The values of these elements are determined by analytical and semiempirical formulas. The model is validated by a full-wave electromagnetic field solver, as well as measurements. The simulated S-parameters of the model agree well with the measured S-parameters of on-chip interconnects with different widths and lengths over a wide frequency range from dc up to 110 GHz.

Design of a Simple Current-Mode Multiplier Topology Using a Single CCCII+

Abstract: In this paper, an analog current-mode (CM) multiplier circuit employing a single plus-type second-generation current-controlled conveyor (CCCII+) and a grounded resistor is proposed. The developed circuit can provide two-quadrant multiplication, four-quadrant multiplication, and frequency doubling all from the same topology with the selection of the applied input currents. In addition to the signal limitations of the multiplier configuration, the nonideality effects of the CCCII+ and the nonideal gain and parasitic impedance effects on the proposed circuit are investigated. The realized circuit is simulated with SPICE to exhibit its performance. In addition, a CM multiplier derived from the proposed multiplier is set up with commercially available active components to easily perform its experimental test.

Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology

Abstract: Two parallel methods of simulation have been developed in order to evaluate the electrostatic impact that a through-silicon via (TSV) may have on a 65 nm MOS transistor. The first model is based on the finite element method (FEM) and the second one is related to electric component models (SPICE language). Both approaches are then compared and discussed. The SPICE model has been calibrated on the numerical one, so that it can be used for more complex devices - here, an inverter - and more systematic investigations. A range of 3D-compatible design rules have been defined. By integrating these new data on a complete 3D design methodology, we are able to design and layout simple logic circuitries based on a 2-stratum 3D architecture.

Experimental study and spice simulation of cmos inverters latch-up effects due to high power microwave interference

Abstract: Experimental study and SPICE simulation of CMOS digital circuits latch-up effects due to high power microwave interference are reported in this paper. As a traditional inherent destruction phenomenon, latch-up effect may jeopardize the correct function of the circuits, and could be triggered in various ways such as ESD pulse, cosmic ray, heavy ion particles etc. Through the directly injected experimental investigation of CMOS inverters, it is shown that the single short high power RF pulse not only could disturb and upset the inverters output logic voltage, but also might trigger CMOS latch-up effects. It is observed that the RF pulse leading to inverters latch-up effects have energy threshold characteristics, which means that the injected RF pulse power is inversely proportional to the pulse width. SPICE simulations indicated that the inverters maximum static consumption current in latch-up state will increase up to 6600 multiples compared to the normal value when input logic state is high. With the device scaling down, higher integration and higher working frequency, the power consumption problem plays a significant role, which makes CMOS logic circuits more vulnerable due to the latch-up effects under high power microwave threats.

An Improved Compact Model of Silicon-Controlled Rectifier (SCR) for Electrostatic Discharge (ESD) Applications

Abstract: This paper describes the development of a SPICE equivalent-circuit model of the silicon-controlled rectifier (SCR) for electrostatic discharge (ESD) protection applications. The framework developed includes the equivalent circuit, models for the various components imbedded in the SCR, and model parameters' extraction. The new model is implemented into the industry standard Cadence SPICE and is verified against transmission line pulsing measured data.

Improved electrothermal model of the thermoelectric generator implemented in SPICE

Abstract: In the paper an improved model of the thermoelectric generator (TEG) is shown. The electrothermal model was implemented into electronic circuits simulator SPICE and it was used during simulation of energy harvesting processes. In the latest version a dependence of the internal electrical resistance of the Peltier module in respect to temperature changes was introduced. Therefore, better accuracy of the model was achieved especially for small gradients of temperatures.

Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model

Abstract: Nanometric SRAMs are more vulnerable to experiencing particle induced soft error due to lower operating voltages coupled with higher packing density and increased process variations. In this paper, we present a compact model for critical charge of a 6T SRAM cell for estimating the effects of process variations on its soft error susceptibility. The model is based on dynamic behavior of the cell and a simple decoupling technique for the non-linearly coupled storage nodes. The model describes the critical charge in terms of transistor parameters, cell supply voltage, and injected current parameters. Consequently, it enables investigating the spread of critical charge due to process induced variations in these parameters and to manufacturing defects, such as, resistive contacts or vias. In addition, the model can estimate the improvement in critical charge when MIM capacitors are added to the cell in order to improve the soft error robustness. The critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90 nm CMOS process with a maximum discrepancy of less than 5%.

Technology independent circuit sizing for fundamental analog circuits using artificial neural networks

Abstract: This study introduces technology independent neural network modeling for fundamental blocks of analog integrated circuits. The circuits modeled here are basic current mirror structures and a differential amplifier which serves as the input stage to most op-amps. Here if a designer defines the output specifications of the circuit, the neural network gives the channel widths (W) of all transistors in the circuit. It must be noted that the neural network in this novel approach is trained with the database including simulations using 1.5 mum, 0.5 mum, 0.35 mum and 0.25 mum technology SPICE parameters and the test data is constituted with simulations using only 0.18 mum technology SPICE parameters which are not applied to the neural network for training beforehand. This shows that neural network is able to give the transistor sizes of circuit for a new unknown technology, independent on the SPICE parameters. As artificial neural network (ANN) structures, General Regression Neural Network (GRNN) and Multilayer Perceptron (MLP) having back propagation algorithm are used. Using new channel widths and lengths obtained from neural networkpsilas output, SPICE simulations of current mirrors and differential amplifier give the desired circuit output specifications for new technology.

SPICE modeling of BCI probes accounting for the frequency-dependent behavior of the ferrite core

Abstract: In this paper, SPICE behavioral modeling of injection probes for bulk current injection (BCI) is addressed. The implementation procedure is based on preliminary experimental characterization of the frequency response of the probe core via measurement of the probe input impedance. Two alternative solutions are proposed for the inclusion of frequency-dependent core-related effects. The first solution directly embeds measurement data of the effective permeability spectra of the ferrite core in a SPICE behavioral module; an alternative solution employs a Lorentzian model. Models accuracy and effectiveness are assessed by comparing SPICE predictions of a simplified BCI setup with experimental measurements.

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out

Abstract: Novel single electron transistor (SET) read-out circuit designs are described The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit The design assumes standard submicron (035 um) CMOS SOI technology using room temperature SPICE models Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches

New SET Characterization Technique Using SPICE for Fully Depleted CMOS/SOI Digital Circuitry

Abstract: The new SET characterization technique for 0.15 mum Fully Depleted CMOS/SOI digital circuitries was investigated using SPICE and TCAD simulations. The SPICE simulation with a switch can readily reproduce the corresponding SET voltage response for a certain LET. This technique is valid as an alternative in all load and complementary transistor conditions, irrespective of the presence of a plateau region in the SET current waveform generated in a struck transistor.

Spice simulation of a large-signal model for quantum cascade laser

Abstract: A large-signal spice model of QCL is described, which is based on a set of rate equations. This model can also perform both small- and large-signal simulations. The dynamic responses obtained by using Spice simulator are obviously different from those in the interband lasers. No resonance peak is presented in the modulation response and the 3-dB bandwidth would reach tens of GHz. The turn-on delay time is on the order of ps that accord with the carrier lifetime of QCL. In addition, the dependency of bias current on the dynamic response are investigated. Results indicates that the bias current has a significant effects on the QC laser.

Inductance formulas adapted for direct use in Spice simulators

Abstract: Accurate analytical formulas for the self and mutual inductance of rectangular wires, that only require basic arithmetic expressions, are presented. The main objective of these formulas is their use as user defined parameterised expressions in Spice and similar applications, offering a convenient way to simulate and optimise the inductive behaviour of on-chip metal wires.

A system-level model for a silicon thermal flow sensor

Abstract: A system-level model with lumped parameters for a thermal flow sensor is presented. The model is built with 13 circuit cells consisting of thermal resistors and thermal capacitors in SPICE. The circuit cell originates from the heat conduction equation using the Finite Differential Method, including the 2-D thermal conduction cell, the convection cell, and the thermal capacity in the chip. Based on the thermal model of the flow sensor, the 2-D temperature distribution of the chip can be calculated with SPICE in both the constant power mode (CP) and constant temperature difference mode (CTD). As an example, the system level model of the thermal anemometer in the CTD mode was established in PSPICE. Wind tunnel test was carried out to verify the system model, and show a reasonable agreement with the simulation results, with an error less than 8%.

Synthetic soft error rate simulation considering neutron-induced single event transient from transistor to LSI-chip level

Abstract: Soft error phenomena induced by the Sea-level cosmic neutron have been investigated by using a simulation system that covers from an individual MOSFET device level to an LSI-chip level. This system consists of the several kinds of simulation codes/tools, such as a mixed-mode 3D device simulator, SPICE circuit simulator, and analyzing tools of gate-level net-lists. A comprehensive practical simulation flow is demonstrated in this paper on commercial 90 nm generation logic devices and standard-cells.

Lumped and Distributed Parameter SPICE Models of TE Devices Considering Temperature Dependent Material Properties

Abstract: Based on simplified one-dimensional steady-state analysis of thermoelectric phenomena and on analogies between thermal and electrical domains, we propose both lumped and distributed parameter electrical models for thermoelectric devices. For lumped parameter models, constant values for material properties are extracted from polynomial fit curves evaluated at different module temperatures (hot side, cold side, average, and mean module temperature). For the case of distributed parameter models, material properties are calculated according to the mean temperature at each segment of a sectioned device. A couple of important advantages of the presented models are that temperature dependence of material properties is considered and that they can be easily simulated using an electronic simulation tool such as SPICE. Comparisons are made between SPICE simulations for a single-pellet module using the proposed models and with numerical simulations carried out with Mathematica software. Results illustrate accuracy of the distributed parameter models and show how inappropriate is to assume, in some cases, constant material parameters for an entire thermoelectric element.

Tunable all-pass filter with a single inverting voltage buffer

Abstract: This paper presents a voltage mode all-pass filter, with a MOSFET transistor, two resistors, a capacitor and an inverting voltage buffer. It is expected to be simpler compared to integrator based MOSFET-C counterparts. The functionality of the proposed circuit is verified with SPICE simulations.

Method for modeling diode multiple simulator format SPICE model

Abstract: The invention discloses a modeling method of a diode SPICE model with various emulator formats, which includes the steps that: the extraction of the diode model parameter with HSPICE emulator format is carried out; the important parameter of the HSPICE emulator format is transformed into the diode model parameter with corresponding SPECTRE emulator format, and the extraction of the diode model parameter in the non-high current injecting area of the SPECTRE emulator format is carried out; the model parameter IKP which generates current distortion of the perimeter part of the diode is added as the model parameter, when the high current is injected, and the extraction of the diode model parameter in the high current injecting area of the SPECTRE emulator format is carried out; the numerical value of the IKP is optimized. The invention can obtain the diode SPICE model with better simulation result and fitness of test data in a short time.

Variation Aware Spline Center and Range Modeling for Analog Circuit Performance

Abstract: With scaling technologies, process variations have increased significantly. This has led to deviations in analog performance from their expected values. Performance macromodeling aids in reduction of synthesis time by removing the simulation overhead. In this work, we develop a novel spline based center and range method (SCRM) for process variation aware performance macro-modeling (VAPMAC) which works on interval valued data. Experiments demonstrate around 200K times computational time advantage using VAPMAC generated macromodels over SPICE Monte Carlo simulation. The results also demonstrate less than 10% loss in accuracy in computing the performance bounds using the macromodels compared to the SPICE simulations.

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations

Abstract: We investigate the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial models cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary continuous function. Our initial experiments with a small subset of standard cell gates of an industrial 65 nm library show promising results with error in mean less than 1%, error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1 V of supply, -40degC to 125degC of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scalable with similar accuracy requires on an average 4x more SPICE characterization runs.

Spice packaging system

Abstract: A spice packaging system is provided that includes a plurality of packets for one or more spices, herbs or spice blends. Each packet includes a flexible packaging material that is impervious to light, gas and moisture. The packet has an exterior and a single or segmented enclosed and sealed interior space. A known volume of a single certified organic spice or herb is contained with the interior space of each packet, and an inert gas surrounds each known volume of the single certified organic spice or herb within the interior space.