Showing papers on "Spice published in 2019"

JoSIM—Superconductor SPICE Simulator

Abstract: We present Josephson simulator (JoSIM), a simulation program with integrated circuit emphasis (SPICE)-based circuit simulator that utilizes the modified nodal voltage analysis method and trapezoidal integration to solve systems of linear equations. The objective of JoSIM is to provide accurate simulation results with major improvement in terms of simulation speed and expandability. JoSIM incorporates the ability to do phase-based simulation through a modified nodal phase analysis method. A full data visualization GUI, built using open-source graphical libraries, is included. We show the results of simulations with JoSIM and compare them to the results of the JSIM, as well as comparisons between simulation times. We also show extremely large simulations, which are not realizable in reasonable time using JSIM.

A Universal SPICE Field-Effect Transistor Model Applied on SiC and GaN Transistors

Abstract: This paper presents a universal SPICE model for field-effect transistors, which is independent from technology and semiconductor material. The created behavioral simulation model is based on a set of collected measurement data. The temperature-dependent output characteristics are modeled using a hybrid approach consisting of lookup tables and analytical equations. This leads to fast simulation times and very high accuracy. The validity for the static temperature-dependent behavior of this approach is verified for one SiC and one GaN transistor using the respective datasheet curves. The transistors nonlinear capacitances are modeled in dependence of their inter-electrode voltages. In order to verify the validity in the dynamic range, the universal model is applied to a GaN high-electron-mobility transistor. Double pulse measurements are used for the dynamic validation at a characterized measurement test bench regarding its parasitic elements. Therewith a proper validation of the simulation model at switching transients as low as 5 ns is achieved.

Novel CFOA based capacitance multiplier and its application

Abstract: This communication presents a novel CFOA based capacitance multiplier. The proposed circuit employs two CFOAs, two resistors and a single capacitor. To achieve higher multiplication factors, the larger component spread is needed in existing CFOA based capacitance multiplier circuits. The proposal addresses this and attains multiplication at lower component spread. The mathematical analysis for modelling the effects of non-ideality shows the deviations from ideal behavior which may be compensated by placing an additional resistor. The functionality is tested using SPICE simulations and experimentation under different conditions. An application namely parallel RLC resonator is included to show the usefulness.

RFI Mitigation for UWB Radar Via Hyperparameter-Free Sparse SPICE Methods

Abstract: Radio frequency interference (RFI) causes serious problems to ultrawideband (UWB) radar operations due to severely degrading radar imaging capability and target detection performance. This paper formulates proper data models and proposes novel methods for effective RFI mitigation. We first apply the single-snapshot Sparse Iterative Covariance-based Estimation (SPICE) algorithm to data from each pulse repetition interval for RFI mitigation and discuss the connection of SPICE to the $l_{1}$ -penalized least absolute deviation ( $l_{1}$ -PLAD) approach. Then, we devise a modified group SPICE algorithm and we prove that it is equivalent to a special case of the $l_{1,2}$ -PLAD method. The modified group SPICE algorithm can be applied to data from a coherent processing interval for effective RFI mitigation. Both the single-snapshot SPICE and the modified group SPICE methods simultaneously exploit the sparsity properties of both RFI spectrum and UWB radar target echoes. Unlike the existing sparsity-based RFI suppression methods, such as the robust principal component analysis algorithm, the proposed methods are hyperparameter-free and therefore easier to use in practical applications. Furthermore, the fast implementation of the SPICE methods is considered by exploiting the special structures of both single-snapshot and multiple-snapshot covariance matrices. Finally, the results obtained from applying the SPICE methods to simulated data as well as measured data collected by the U.S. Army Research Laboratory synthetic aperture radar system are presented to demonstrate the effectiveness of the proposed methods.

A 1-V Bandgap Reference in 7-nm FinFET With a Programmable Temperature Coefficient and Inaccuracy of ±0.2% From −45°C to 125°C

Abstract: We present a 1-V precision voltage reference with a programmable temperature coefficient (“ temp-co ”). The voltage reference is based on a parasitic bipolar junction transistor (BJT) realized within the process steps available in the chosen 7-nm FinFET technology. Details of its characterization and SPICE modeling are presented to provide insight into key device–circuit optimization choices. The trimming techniques needed to cope with process spread together with two curvature compensation techniques are presented. The reference achieves a maximum inaccuracy of ±0.2% and a minimum temp-co of 6 ppm/°C from −45°C to 125°C. Furthermore, its temp-co is digitally programmable between −7 mV/100°C and +8 mV/100°C. Its line regulation is 0.1%/V, and it occupies 0.078 mm2.

Symbiotic organisms search algorithm for optimal design of CMOS two-stage op-amp with nulling resistor and robust bias circuit

Abstract: This study suggests an evolutionary technique namely symbiotic organisms search (SOS) algorithm based optimal designs of two different analogue very-large-scale integration circuits. The configurations considered here are nulling resistor compensation based complementary metal–oxide–semiconductor (CMOS) two-stage op-amp and two-stage CMOS op-amp with robust bias circuit. The prime goal of this work is the sizing of metal–oxide–semiconductor (MOS) transistors employing the SOS algorithm to optimise the area occupied by the individual circuit. Design results based on the SOS algorithm are authenticated with SPICE simulation. SPICE simulation results reveal that all the design specifications are firmly satisfied for both the circuits. Moreover, SPICE based results show that the SOS algorithm provides much better results compared to the earlier reported techniques regarding the gain, MOS area and power dissipation for the abovementioned op-amp circuits.

SPICE Model Identification Technique of a Cheap Thermoelectric Cell Applied to DC/DC Design with MPPT Algorithm for Low-Cost, Low-Power Energy Harvesting

Abstract: In this work, an identification technique of a simple, measurements-based SPICE (Simulation Program with Integrated Circuit Emphasis) model is presented for small low-cost Peltier cells used in thermoelectric generator (TEG) mode for low-temperature differences. The collection of electric energy from thermal sources is an alternative solution of great interests to the problem of energy supply for low-power portable devices. However, materials with thermoelectric characteristics specifically designed for this purpose are generally expensive and therefore often not usable for low cost and low power applications. For these reasons, in this paper, we studied the possibility of exploiting small Peltier cells in TEG mode and a method to maximize the efficiency of these objects in energy conversion and storage since they are economical, easy to use, and available with different characteristics on the market. The identification of an accurate model is a key aspect for the design of the DC/DC converter, in order to guarantee maximum efficiency. For this purpose, the SPICE model has been validated and used in a design example of a DC/DC converter with maximum power point tracking (MPPT) algorithm with fractional open-circuit voltage. The results showed that it is possible to obtain a maximum power of 309 µW with a Peltier cell 2 × 2 cm at a ΔT of 16 °C and the designed SPICE DC/DC converter performance proved the improvement and optimization value given by the TEG model identification.

Measurement and Analysis of Statistical IC Operation Errors in a Memory Module Due to System-Level ESD Noise

Abstract: Voltage noise and operation errors in an integrated circuit (IC) due to electrostatic discharge (ESD) events were measured, validated, and analyzed in this paper. A simplified structure of a laptop personal computer and an IC with a D-type flip-flop were designed and manufactured for the experimental tests. Every signal input to the IC was simultaneously measured during the ESD tests, and validated with the simulated results using a full-wave solver and a simple circuit model. Next, SPICE simulations were conducted using the measured voltages with ESD tests. The output waveforms and the statistical occurrence ratios of the operation failures found from the SPICE simulations were compared with measured values. Furthermore, the effects of decoupling capacitors on the IC operation failures due to ESD were investigated.

Adaptation of a compact SPICE level 3 model for oxide thin-film transistors

Abstract: Oxide thin-film transistors (TFTs) and metal–oxide–semiconductor field-effect transistors (MOSFETs) operate via different conduction mechanisms but exhibit similar device characteristics. In this work, a SPICE level 3 model originally defined for MOSFETs is successfully adapted to provide a behavioral model for oxide TFTs. This adapted compact model is applicable to all kinds of oxide TFTs, irrespective of the channel and dielectric material used. To capture the TFT behavior efficiently, the experimental characteristic of an oxide TFT is used to set various SPICE level 3 parameters.

Voltage-mode third-order quadrature sinusoidal oscillator using VDIBAs

Abstract: A third-order quadrature sinusoidal oscillator (TOQSO) is proposed employing two voltage differencing inverting buffered amplifiers (VDIBAs), three grounded capacitors and a resistor. The proposed TOQSO enjoys electronically tunable, non-interactive condition and frequency control. The TOQSO uses all grounded capacitors, which is suitable for IC implementation. Moreover, the internal CMOS realization of VDIBA is possibly the simplest among all recently introduced new active building blocks. SPICE simulation results have been provided to support the validity of proposed TOQSO using TSMC 0.18 µm technology.

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Abstract: In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can automatically generate Verilog and SPICE netlists based on realistic FPGA configurations and a high-level eTtensible Markup Language-based FPGA architectural description language. The outputted Verilog netlists can be used to generate layouts of full FPGA fabrics through a semicustom design flow. SPICE simulation decks can be generated at three levels of complexity, namely, full-chip-level, grid-level, and component-level, providing different tradeoff between accuracy and simulation time. In order to enable such level of analysis, we presented two SPICE netlist partitioning techniques: loads extraction and parasitic net activity estimation. Electrical simulations showed that averaged over the selected benchmarks, the grid-/component-level approach can achieve $6.1\times /7.5\times $ execution speed-up with 9.9%/8.3% accuracy loss, respectively, compared to the full-chip level simulation. FPGA-SPICE was showcased through three different case studies: 1) an area breakdown analysis for static random access memory-based FPGAs, showing that configuration memories are a dominant factor; 2) a power breakdown comparison to analytical models, analyzing the source of accuracy loss; and 3) a robustness evaluation against process corners, studying their impact on energy consumption of full FPGA fabrics.

Large-signal SPICE model for depletion-type silicon ring modulators

Abstract: We present an accurate, easy-to-use large-signal SPICE circuit model for depletion-type silicon ring modulators (Si RMs). Our model includes both the electrical and optical characteristics of the Si RM and consists of circuit elements whose values change depending on modulation voltages. The accuracy of our model is confirmed by comparing the SPICE simulation results of 25 Gb/s non-return-to-zero (NRZ) modulation with the measurement. The model is used for performance optimization of monolithically integrated Si photonic NRZ and pulse-amplitude-modulation 4 transmitters in the standard SPICE circuit design environment.

SPICE Modeling of Insulator Metal Transition: Model of the Critical Temperature

Abstract: This paper proposes a compact SPICE phenomenological model for insulator metal transition (IMT) devices. The proposed model captures the interplay of electric field and Joule heating to effect a transition from a high resistance insulating state to a low resistance metallic state. The model is corroborated against experimental results and electrothermal simulations available in the literature. The proposed model is implemented in Verilog-A and is fully compatible with commercial SPICE simulators such as Spectre from Cadence, used in this paper. An IMT-based artificial neuron is then designed and simulated using the proposed IMT compact model and design expressions for the operation of the proposed neuron are derived. The simulation results agree with the expected neuron behavior as well as the simulation results of other similar neurons proposed in the literature. This paper will enable circuit designers to design and simulate IMT-based systems and help them explore the full potential of such novel devices.

Modeling and Analysis of Large-Signal RFI Effects in MOS Transistors

Abstract: The ability of radio-frequency (RF) interference signals to upset or disrupt electronic equipment is a matter of concern, and identification of the physical mechanisms leading to device malfunction is of prime importance. This paper presents experimental and theoretical results and analyzes the effects of a large-signal microwave excitation up to 2 GHz on several commercial small-signal MOS transistors. For frequencies beyond the maximum operating frequency, experimental results show RF signal rectification in the devices, and these results are confirmed by SPICE simulations using extracted models for the transistors, including package and test circuit parasitics, with excellent agreement with experiments. Analysis of internal transistors currents and voltages finally leads to the conclusion that the observed rectification effect is not due to active nonlinearities of the devices, but rather due to the nonlinear overlap and parasitic drain–bulk diode capacitances of the MOS transistors. In particular, the role of the nonlinear voltage dependence of the junction capacitance is highlighted. Finally, a simplified model is proposed to reproduce this behavior.

Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms

Abstract: In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.

CMOS Class AB Second Generation Voltage Conveyor

Abstract: This paper presents a class AB second generation voltage conveyor. This device is designed to obtain the current buffer as input stage and is followed by the voltage buffer in monolithic chip. A class AB technique to obtaining high signal swing, high dynamic range, high bandwidth and low power consumption has been used. The proposed circuit is simulated using SPICE simulations with a standard $0.18 \ \mu m$ CMOS process and with $\pm 0.9\mathrm{V}$ supply.

Bulk-driven fully balanced second-generation current conveyor in 0.18 µm CMOS

Abstract: This paper presents an ultra-low-voltage and low-power fully balanced second-generation current conveyor (FBCCII) which is suitable for applications in ultra-low-voltage and low-power analog circuits. To confirm the attractive features of proposed FBCCII, the analog circuits such as fully digital programmable voltage gain amplifier, fully all-pass sections, fully band-pass filter and fully universal filter using the proposed FBCCII as active element have been proposed. The performances of the proposed FBCCII and its applications can be depicted through simulation results using SPICE simulations and 0.18 µm n-well CMOS process from TSMC with a 0.5 V supply.

RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer

Abstract: A physical design methodology is presented to synchronize digital application specific integrated circuit (ASIC) designs by a resonant rotary clock network. One novelty of the proposed RotaSYN flow is that the ASIC products of RotaSYN can operate at previously unattainable (relatively) low-frequency ranges of hundreds of megahertz. The dynamic resonant frequency divider is used to implement the low-frequency operation; and low in comparison to the norm of gigahertz-range of operation for resonant clocking reported in this paper. In SPICE -based simulations, the efficacy of the proposed flow and novel algorithms in RotaSYN is demonstrated using performance metrics of the wirelength, skew, and power on international symposium on physical design-10 clock benchmark circuits. In addition, RotaSYN is compared to three publicly available industrial designs that include the ARM Cortex M0 against equivalent clocks generated with a traditional phase locked loop (PLL) and distributed with an industrial clock tree synthesis tool flow. The RotaSYN methodology is implemented at three different target frequencies of 880 MHz, 500 MHz, and 220 MHz for the industrial designs. SPICE simulations show an average of 29% power savings for the industrial designs overall, solely thanks to 66% power savings on the clock generation and distribution networks, operating at a frequency of 880 MHz on comparison to the PLL-based design with a clock tree synthesized with an industrial EDA tool.

More Accurate Miller Capacitor Modeling for SiC Switching Characteristic Prediction in High Frequency Applications

Abstract: A more accurate miller capacitor model is proposed in this paper to achieve precise SiC switching characteristic prediction for high frequency and high power density designs. The SPICE models of power transistors are either not provided or fail to represent parasitic capacitor accurately, which will lead to poor estimation of device switching loss. For SiC transistor used in this paper, LTSPICE simulation shows up to 53.7% mismatch in miller capacitor compared with measurement data provided in datasheet. Accurate switching loss prediction will help to use SiC more effectively and thermally optimized in high frequency, high power density systems. The physical mechanism of miller capacitor reflects an internal cascaded configuration of a fixed capacitor with a voltage depended capacitor. The voltage depended capacitance is further influenced by different doping concentrations in vertical power MOSFET and can be splitted into four stages. Based upon these, the Segmented-and-Cascaded miller capacitor approximation method is proposed. It shows descent agreement with datasheet C-V curve of less than 15% mismatch, which is three times less than SiC SPICE model. Experimental results using double pulse test circuit are provided to verify the proposed miller capacitor model. The maximum mismatches under hard switching at 500V are 9.5% for dv/dt and 8.4% for di/dt.

Fast and accurate PV model for SPICE simulation

Abstract: This paper presents a complete model for photovoltaic modules able to accurately predict the I–V characteristics at different levels of temperature and irradiance. The model greatly reduces the computational effort needed to extract the five parameters of the one-diode model by applying five boundary conditions based on data provided by the manufacturer only. The model equations are reduced to only two simultaneous equations of two unknowns (series resistance, $$R_\mathrm{s}$$ , and shunt resistance, $$R_\mathrm{sh}$$ ), which converge in five iterations on average. The model parameters are extrapolated to account for temperature and irradiance variations. The model is matched very well with the experimental data obtained from different commercial PV modules. The proposed I–V model has least root mean square error of (0.0031) compared to other works. The model is implemented in Verilog-A to be used inside SPICE simulators. The model in Verilog-A is integrated in Cadence-SPECTRE circuit simulator and tested with a boost converter.

A Particle Detector Based on Pulse Stretching Inverter Chain

Abstract: Monitoring of energetic particles responsible for the soft errors is an important requirement in the design of fault-tolerant systems for space missions. In this paper, the use of a custom-sized CMOS pulse stretching inverter chain as a particle detector is studied. The proposed detector allows for measuring the particle flux in terms of the count rate of induced Single Event Transients (SETs). In contrast to the conventional SRAM-based detectors, the proposed solution is potentially more sensitive to particle strikes, requires simpler processing logic and is more immune to multiple errors and error accumulation. The concept has been evaluated with SPICE simulations for the IHP's 130 nm CMOS technology. The target applications are the self-adaptive multi-processor systems, where the particle detector can be used to dynamically trigger the fault-tolerant mechanisms.

SPICE Models for one-conductor and three-conductor lines excited by a uniform plane wave

Abstract: This paper presents SPICE models for one-conductor line over a ground plane and three-conductor lines excited by an incident uniform plane wave. The models can be used to predict the voltage and current response at the terminations of the conductors. They take into account the boundary conditions at the line ends and can thus be integrated into simulations for EMC analysis. A plane wave is represented in the form of a voltage source feeding the model. Model validation is applied in time and frequency domain. The results are compared to a SPICE model from another source and a numerical simulation. Very good agreement can be observed.

Voltage Differencing Buffered Amplifier based Voltage Mode Four Quadrant Analog Multiplier and its Applications

Abstract: In this paper a voltage mode four quadrant analog multiplier (FQAM) using voltage differencing buffered amplifier (VDBA) based on quarter square algebraic identity is presented. In the proposed FQAM the passive resistor can be implemented using MOSFETs operating in saturationregion thereby making it suitable for integration. The effect of non idealities of VDBA has also been analyzed in this paper. Theoretical propositions are verified through SPICE simulations at 0.18μm CMOS technology node and the simulation results are found in close agreement with theoretical values. The supply voltage is taken as ± 1V and the value of the bias current is set to 40µA.The simulated total harmonic distortion (THD) is observed to be under 3% and the total power dissipation is found as 627µW. The workability of the proposed FQAM is also tested through two applications, namely, an amplitude modulator and a rectifier. The simulated results corroborate the theoretical propositions.

Broadband TCAD mixed-mode simulation framework for predictive modeling of fast dynamic switching events

Abstract: In this paper, we develop a simulation framework for analyzing and optimizing the large signal, dynamic switching behavior of power devices. This framework enables us to use TCAD models of our active devices, together with a broadband description of the application board. All elements are coupled through a mixed-mode SPICE instance. Simulated results, obtained with this new method for two application boards, are compared to measurement data and their agreement is analyzed.

An Improved SPICE Model of SiC BJT Incorporating Surface Recombination Effect

Abstract: The SiC bipolar junction transistor (BJT) offers an attractive alternative to the more popular SiC mosfet . It is important to develop an accurate SPICE model for the SiC BJT to enable its use in power electronic applications. The current gain of an SiC BJT may degrade considerably at high current levels and/or at high temperatures largely due to the surface recombination effect. In this paper, an improved SPICE behavioral model that accurately accounts for the current gain depending on the collector current and the junction temperature is proposed for the SiC BJT. In this paper, the conventional Gummel–Poon model is extended to include this important physical effect by adding a diode between the external base and emitter terminals of the BJT. A two-step model parameter extraction method is developed. First, the basic Gummel–Poon model parameters are extracted from low-current measurement data, and then, the new surface recombination model parameters are extracted by observing the difference between the measured high-level base current and the standard Gummel–Poon model prediction. The simulated static and switching characteristics of the new SiC BJT model match the measured data very well. Finally, the new SPICE model is used in the performance assessment of a proportional base driver technique embedded in a 3.6-kW boost converter, demonstrating its validity in helping with the optimum design of power electronic applications based on SiC BJTs.

A Practical HfO 2 -based OxRAM Memristor Model Suitable for Circuit Design and Simulation

Abstract: CMOS technologies are attending their limits due to its continuous shrinking process, which has an impact on various aspects, accurately on the size, performance and power consumption of the device. One of the promising devices known as memristor is under investigation in order to be used together with deep nanometer CMOS, that has the ability to solve technologies problems. It has emerged in several domains due to its nonlinear behavior, nonvolatility, low power consumption, high density and compatibility with CMOS. Several memristor models have been developed so far. Whereas, a compact model should be flexible and sufficiently accurate. In this paper, an analysis of a memristor model using Verilog-A and SPICE is discussed, in order to elaborate an appropriate model for implementation in CMOS-based circuit applications. It is shown that the proposed Verilog-A model is flexible, accurate and efficient, verified by both electrical simulations and experimentally measured results. It also carries the desired nonlinear memristor fingerprint, an adjustable threshold voltage and the applicability to fit and simulate different switching behaviors. Hence, it is the most suitable for low-power and high-density applications at the industrial levels, which takes advantage compared to other approaches based on SPICE models.

State-variable and cyclic-averaging analysis of bidirectional CLLC resonant converters

Abstract: The study proposes the application of state variable and cyclic-averaging modelling techniques for analysis of bidirectional, dual active bridge, CLLC resonant converters. The techniques are applied for converters operating under single phase-shift modulation in forward and reverse modes and the equation description is obtained for both models. The design of the converter is presented and the simulation results obtained are compared to a Spice-based simulation to verify the accuracy of the proposed models. Results show the models are suitable to represent the behaviour of CLLC converters under single phase-shift modulation. In addition, when using the cyclic-averaging technique integration is not required to solve the model, which results in a considerably rapid analysis when compared to the execution times of state variable and Spice-based models.

Process Variation-Aware Analytical Modeling of Subthreshold Leakage Power

Abstract: Leakage current is making a substantial contribution to the power dissipation in nanometer regime due to continued technology scaling. The problem is further accentuated with the increasing levels of unpredictability in process parameters. Consequently, accurate and reliable modeling of leakage current is critical for the prediction of static power, especially for ultra low power applications. In contrast to gate leakage and Band-to-Band-Tunneling (BTBT) leakage, subthreshold leakage is the most sensitive to parameter variations and hence has been considered for variability modeling. The variations in electrical and geometry parameters of the device drastically impact the sub-threshold leakage current. In this paper, a subthreshold leakage power estimation model in the presence of process variations, with Drain-Induced Barrier Lowering (DIBL) considerations, is proposed. The model focuses on the subthreshold leakage variations induced by the simultaneous effect of threshold voltage variability and variations in gate length and width. The variation in the subthreshold leakage power is characterized by using an extensive Monte Carlo analysis. In order to demonstrate the efficacy of the proposed model, the model generated distributions of a static CMOS inverter are overlaid on the SPICE generated distributions in 32 nm PTM technology. The results demonstrate that, in the presence of process variations, the proposed model offers better predictability with a mean error in the range of 0.09% to 0.45% and reduction in the standard deviation of 3.3% to 34%, resulting in tighter distributions, thereby ensuring better predictability and design robustness. Further, the proposed model is about 700X computationally faster than SPICE simulations.