Showing papers on "Spice published in 2020"

Nonlinear Compact Thermal Model of the IGBT Dedicated to SPICE

Abstract: In this article, the problem of modeling the thermal properties of the IGBT using a nonlinear compact thermal model is considered. This model has the form of an electrical network. In the proposed model, the influence of the internal temperature of this transistor on the efficiency of heat dissipation is taken into account. The elaborated model form is presented and the estimation method of this model parameters is described. The correctness of the new model is verified experimentally for different cooling conditions and different values of ambient temperature. Additionally, some results of calculations are compared to the results of calculations performed using selected models given in the literature.

Extreme Temperature Modeling of AlGaN/GaN HEMTs

Abstract: The industry standard advanced SPICE model (ASM)-GaN compact model has been enhanced to model the GaN high electron mobility transistors (HEMTs) at extreme temperature conditions. In particular, the temperature dependence of the trapping behavior has been considered and a simplifying approximation in the temperature modeling of the saturation voltage in the ASM-GaN model has been relaxed. The enhanced model has been validated by comparing the simulation results of the model with the dc ${I}$ – ${V}$ measurement results of a GaN HEMT measured with chuck temperatures ranging from 22 °C to 500 °C. A detailed description of the modeling approach is presented. The new formulation of the ASM-GaN compact model can be used to simulate the circuits designed for extreme temperature environments.

Computational Efficiency Analysis of SiC MOSFET Models in SPICE: Dynamic Behavior

Abstract: Transient simulation of complex converter topologies is a challenging problem, especially in detailed analysis tools like SPICE. Transistor models presented for SPICE are often evaluated by accuracy, with less consideration for the computational cost of model elements. In order to optimize models for application simulations, this research quantifies the relative simulation performance of modeling approaches and contextualizes the results with regard to accuracy. It is well established that the primary contributor to semiconductor dynamic behavior is the voltage-dependent interelectrode capacitances. Therefore, this study isolates these model components to resolve their influence on model accuracy and run-time. Both the voltage-dependencies modeled, and the mathematic formulation chosen strongly influence the accuracy of interelectrode capacitance models. In addition to these factors, the specific implementation chosen within SPICE also determines simulation performance. Through careful evaluation of these factors, this study offers specific recommendations for optimal implementations of interelectrode capacitances in SPICE.

New mixed-mode second-generation voltage conveyor based first-order all-pass filter

Abstract: A new plus-type second-generation voltage conveyor (VCII+) based first-order mixed-mode (MM) all-pass (AP) filter is proposed in this study. The proposed MM AP filter employs two VCII+s, three resistors and one grounded capacitor. It has low input and high output impedances for the current-mode selection while it has low input and low output impedances for the transimpedance-mode selection. The AP filter gain is unity for the current output while it is adjustable for the voltage output via a grounded resistor. However, a single passive component matching condition is needed for the proposed MM AP filter. Complete non-ideal analysis by taking into account all the parasitic resistors and non-ideal gains of the VCII+ is performed. The presented theory is verified through SPICE simulations by using supply voltage of ± 0.9 V and 0.18 μm Taiwan Semiconductor Manufacturing Company complementary metal oxide semiconductor technology parameters.

A Compact Phase Change Memory Model With Dynamic State Variables

Abstract: A SPICE model for phase change memories (PCM) without relying on macro modules is developed in this work. The crystal fraction, physical geometry, and the conduction path of the amorphous region are treated as dynamic state variables to keep track of the memory cell status during SET and RESET. The memory cell resistance is calculated based on a detail 3-D resistance model to capture its transitional behavior during switching. The detail physical formulation correctly reproduced a recent observation of oscillation during the SET operation. The model has been implemented in SPICE, and the convergence of the model is demonstrated by simulations of a complete PCM array. The use of dynamic state variables also significantly reduces the number of internal nodes to one, which helps convergence and reduces the simulation time.

A Theoretical Study of Multidomain Ferroelectric Switching Dynamics With a Physics-Based SPICE Circuit Model for Phase-Field Simulations

Abstract: In this article, the multidomain nature of ferroelectric (FE) polarization switching dynamics in a metal–ferroelectric–metal (MFM) capacitor is explored through a physics-based phase-field approach, where the 3-D time-dependent Ginzburg–Landau (TDGL) equation and Poisson’s equation are self-consistently solved with the SPICE simulator. Systematically calibrated based on the experimental measurements, the model well captures transient negative capacitance (NC) in pulse switching dynamics, with domain interaction and viscosity being the key parameters. It is found that the influence of pulse amplitudes on voltage transient behaviors can be attributed to the fact that the FE free energy profile strongly depends on how the domains interact. In addition, we extract the domain viscosity dynamics during polarization switching according to the experimental measurements. For the first time, a physics-based circuit-compatible SPICE model for multidomain phase-field simulations is established to reveal the impact of domain interaction on the NC effect and microscopic domain evolution. The findings of this article may have important implications for the charge boost induced by the stabilization of NC in an FE/dielectric (DE) stack since the so-called capacitance matching needs to be designed at a specific operating voltage or frequency.

Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport

Abstract: In this article, we propose a compact model for Negative Capacitance Nanosheet Field Effect Transistor (NC-NSFET) including quasi-ballistic transport for sub-7nm technology node. The model captures the electrical characteristics of NC-NSFET for different ferroelectric thicknesses. Further, it captures the reverse short channel effects of NCFET for different channel lengths with a single set of parameters. Also, we build a model for terminal charges of NC-NSFET using the core model and the earlier developed inner fringing charge model. Using our physics-based model, we find that quasi ballistic transport worsens the capacitance matching in NCFET compared to drift-diffusion only case. We validate the compact model for the drain current and the terminal charges with the TCAD results. The proposed compact model is computationally efficient and implemented in the Verilog-A code to enable SPICE circuit simulations. Finally, we demonstrate this by applying our model for NC-NSFET based CMOS inverter and SRAM circuit implementations in SPICE.

An Electrothermal Model for IGBT Based on Finite Differential Method

Abstract: In this article, a practical electrothermal SPICE model is proposed based on finite differential method. Other than the conventional Fourier model and the Hefner model, the distribution of excess carriers can be accurately solved by a finite differential method in the SPICE simulation tool. In this method, the electrothermal behavior of the device is modeled by using a semi-mathematic model. In order to verify the modeling results, a self-packaging insulated-gate bipolar transistor (IGBT) module is tested in both static characteristics and dynamic characteristics, and the simulation results of the presented model fit well with the experimental results under different junction temperatures. More importantly, the finite differential method provided in this article is an approach for modeling bipolar devices, and it can also be applied to model widebandgap devices such as a SiC IGBT and a SiC BJT.

Investigation of device-circuit for negative capacitance vertical nanowire FETs based on SPICE model

Abstract: In this study, a SPICE model for negative capacitance vertical nanowire field-effect-transistor (NC VNW-FET) based on BSIM-CMG model and Landau-Khalatnikov (LK) equation was presented. Suffering from the limitation of short gate length there is lack of controllable and integrative structures for high performance NC VNW-FETs. A new kind of structure was proposed for NC VNW-FETs at sub-3nm node. Moreover, in order to understand and improve NC VNW-FETs, the S-shaped polarization-voltage curve (S-curve) was divided into four regions and some new design rules were proposed. By using the SPICE model, device-circuit co-optimization was implemented. The co-design of gate work function (WF) and NC was investigated. A ring oscillator was simulated to analyze the circuit energy-delay, and it shown that significant energy reduction, up to 88%, at iso-delay for NC VNW-FETs at low supply voltage can be achieved. This study gives a credible method to analysis the performance of NC based devices and circuits and reveals the potential of NC VNW-FETs in low-power applications.

SiC MOSFET Corner and Statistical SPICE Model Generation

Abstract: This paper presents a novel approach to generate corner and statistical SPICE models for SiC MOSFETs The technique is derived from the mature IC industry standard approach known as Backward Propagation of Variance Physically based, scalable SiC MOSFET SPICE models are required to simulate the correlations between electrical specifications and process variations The methodologies presented are applicable to other power discrete devices such as super-junction MOSFETs, IGBTs, and GaN HEMTs

Extremely low-voltage low-power differential difference current conveyor using multiple-input bulk-driven technique

Abstract: In this paper, a new differential difference current conveyor (DDCC) with ultra-low voltage and low-power capability is presented. The DDCC is designed by using a non-tailed differential pair with multiple-input bulk-driven MOS transistor technique to obtain a rail-to-rail input common-mode swing and extremely low supply voltage. The MOS transistors biased in the sub-threshold region have been used to achieve extremely low power consumption. The performance of the proposed DDCC is evaluated by simulation results using SPICE program and MOS transistors parameters provided by a standard n-well 0.18 µm CMOS process from TSMC. A rail-to-rail input common-mode range was shown and a high accuracy was expressed. The bandwidth was 2.2 kHz and the total harmonic distortion was 1% for an input signal with amplitude of 240 mVp-p, obtained at supply voltage of 0.3 V and power dissipation of 28.6 nW. The proposed DDCC has been used to realize a sixth-order low-pass filter for application to electrocardiogram (ECG) applications.

A SPICE-Compatible Equivalent-Circuit Model of Schottky Type p-GaN Gate Power HEMTs with Dynamic Threshold Voltage

Abstract: In this work, an equivalent-circuit model of Schottky type p-GaN gate power HEMT is proposed and demonstrated using SPICE tools The SPICE model takes the distinct underlying physics of the p-GaN gate structure into consideration and precisely captures the dynamic threshold voltage (V TH ) phenomenon The dynamic V TH is an intrinsic property of p-GaN gate HEMT with a Schottky gate contact and is rooted in the fact that the p-GaN layer is floating The floating p-GaN exhibits a charge storage effect in which it requires higher gate voltage to turn on the transistor from a high-voltage off-state than what is expected from the static device characteristics; thus the dynamic V TH is a function of the amount of stored charge The equivalent model in this work is built according to the charge storage process The simulated dynamic device characteristics agree well with the experimental results The influences of the dynamic V TH on the waveforms of power switching circuits are predicted and experimentally verified

Generation of OTRA-Based Inverse All Pass and Inverse Band Reject Filters

Abstract: By utilizing two new operational transresistance amplifier (OTRA)-based generic configurations, we have discussed ten second-order inverse band reject filter circuits and 12 inverse all pass filter circuits. The usability of the inverse filter configurations has been established by SPICE simulations and also by hardware experimentation. In these experiments, integrated circuit from analogue devices, namely AD844-type current feedback operational amplifier, has been used to realize the behaviour of OTRA.

Mathematical Modelling of Inductor Current in Class-D Amplifier for Wireless Power Transfer

Abstract: Class-D power amplifier (PA) driving the primary coil of a wireless power transfer (WPT) system is analyzed. Switching-frequency modulation is used to adjust the PA transmission power to compensate for coupling and loading variations. The respective inductor currents of the primary coil working at resonant, harmonic and sub-harmonic frequencies are analytically derived and verified by extensive SPICE simulations.

Improved SiC MOSFET SPICE Model to Avoid Convergence Errors

Abstract: This paper presents improvements to a SPICE model for a commercially available SiC MOSFET to avoid convergence errors while still providing reliable simulation results. Functionality in the internal part of the model that shapes the transconductance of the device according to its junction temperature and gate-source voltage dependency has been improved to provide a continuous characteristic rather than the initial discontinuous performance. Furthermore, the output characteristics from the initial and the proposed model have been compared to lab measurements of an actual device. The results show that the proposed and initial model provide equally reliable simulation results. However, the proposed model does not run into convergence problems.

A parametric SPICE model for the simulation of spark gap switches.

Abstract: The use of SPICE-based software for the simulation of pulsed power systems—even large complex systems—has become commonplace in the pulsed power community. This is in contrast to earlier work in the field that relied on specially developed simulation codes such as Sandia’s Screamer or the Navy Research Lab’s Bertha, which natively incorporated models for common pulsed power components such as spark gap switches. Unlike these programs, SPICE programs provide a simple and familiar user interface and wide availability. However, SPICE programs do not include realistic models for key pulsed power circuit devices—including the spark gap switch. While simple switch models do exist in SPICE programs, these can only crudely approximate the behavior of a spark gap. This effort focuses on developing an SPICE circuit model for a gas-filled spark gap switch that is physically realistic while being simple enough to permit simulations to run in reasonable times on typical personal computers. Detailed information is provided for implementation in two common versions of SPICE: LTspice and Orcad PSPICE. Adaptation to other SPICE programs is possible with minimal modification. The model is intended as a design tool that uses physical parameters as inputs to connect it directly to the development of useable pulsed power systems. Data collected from the operation of a high-pressure pulsed-charged switch and a complete 12-stage Marx generator have been used to demonstrate the implementation and accuracy of the model over a wide range of parameters.

SPICE-Based Lumped Circuit Model of Shielded Cables for EMC Analyses

Abstract: This paper presents a SPICE-based network model for a coaxial cable with braided shielding over a ground plane. The model can calculate the voltage response at the loads due to the coupling of plane waves or due to lumped interference sources. The cable is represented as cascaded cells with lumped elements and controlled sources. The cells in the inner and outer system are individually coupled by voltage-controlled sources and the mutual inductance. The model can be used in the frequency domain or in the time domain with non-linear elements. The results agree very well with those that were carried out with field simulations.

Cauer-Equivalent Circuit for Inductors Considering Hysteresis Magnetic Properties for SPICE Simulation

Abstract: This article presents a new method to synthesize the Cauer-equivalent circuit for inductors that can represent the hysteresis, eddy current, anomalous core losses, dc and ac winding losses as well as inductance. Only the measurement of inductor loss under the sinusoidal excitation is required to synthesize the SPICE loss model. The proposed circuit model can be used to evaluate the loss under arbitrary voltage/current excitations. In the proposed approach, the measured loss is subdivided into the ac and hysteresis losses. Then, the Cauer-equivalent circuit for SPICE simulation is synthesized from the loss model. It is shown that the losses evaluated by the proposed model are in good agreement with the measured results under the condition of the sinusoidal and triangular cases with and without dc bias current.

Measurement and Analysis of System-Level ESD-Induced Jitter in a Delay-Locked Loop

Abstract: A delay-locked loop (DLL), which is widely used to compensate for the timing of high-speed data communications, was designed and fabricated in a 180 nm CMOS process. The DLL integrated circuit was assembled on a simplified motherboard and the module structures of a laptop computer and was tested under electrostatic discharge (ESD) events. The input and output voltages of the DLL under ESD-induced noises were measured, and the average values of peak-to-peak jitter and jitter durations of the DLL clock were obtained from repeated measurements. The effects of the voltage-drain-drain (VDD) decoupling capacitors and a bias decoupling capacitor were investigated. SPICE simulations were conducted using the measured input voltages and were compared with the measured results. The root causes of the ESD-induced DLL jitter were identified by analyzing the waveforms from the SPICE simulations. Employing VDD decoupling capacitors and maintaining the amount of delay control parameters for delay cells in the DLL were crucial in reducing jitter. The measured ESD-induced VDD noises were also validated and analyzed using impedance parameter measurements.

Stochastic and novel generic scalable window function-based deterministic memristor SPICE model comparison and implementation for synaptic circuit design

Abstract: A memristor is a nonlinear polarity-dependent fundamental circuit element. Due to these intrinsic properties of the device, analyzing a circuit that contains multiple memristors becomes complex. In this paper, we study the characteristics of multiple-memristor series (anti-series) and parallel (anti-parallel) connections, including their transient and stable state composite properties. Also, the existing phenomenological and physics-based memristor mathematical modeling techniques have been discussed for use in SPICE simulation environment. For making a standardized comparison between memristor stochastic and deterministic models, all models presented in this paper have been implemented in a single SPICE program. In addition to the well-known previously reported Joglekar and Biolek window functions, a modified Biolek window function and a novel generic scalable window function have been used to model the intrinsic nonlinearity of memristors effectively. Furthermore, electronic synapse circuits based on memristive devices in series and parallel connections and synaptic circuits based on CMOS transistor–memristor architecture have been presented and analyzed. Based on the obtained results, artificial synaptic circuit design limitation using a single memristor has been demonstrated.

Technical solutions and SPICE modelling of optical sensors

Abstract: Paper represents the technical and circuit solutions of optoelectronic sensors designing. The noise in information signal such as a parasitic effect of external (non-informative) optical radiation and electromagnetic interference could be decreased using hardware and software \"GIRATO\" package. The main results of this implementation by using SPICE simulation was carried out in our paper. Streszczenie. Artykuł przedstawia rozwiązania techniczne i układowe w zakresie projektowania czujników optoelektronicznych. Szumy w sygnale informacyjnym, takie jak pasożytniczy efekt zewnętrznego (nieinformacyjnego) promieniowania optycznego i zakłóceń elektromagnetycznych, mogą być zmniejszone za pomocą pakietu sprzętowego i programowego \"GIRATO\". Główne wyniki tej realizacji z wykorzystaniem symulacji SPICE zostały przedstawione w naszym artykule. (Rozwiązania techniczne i modelowanie czujników optycznych z użyciem SPICE).

Massively Parallel Circuit Setup in GPU-SPICE

Abstract: SPICE simulations are the industry standard to analyze circuits for decades. However, they are computationally complex as each circuit is simulated at the transistor-level. However, this is in a direct conflict with the ever-increasing demands of circuit designers in which SPICE simulations for large circuits (e.g., DSPs, AES, etc.) at full accuracy are inevitably required to fulfill new industrial standards like automotive safety ISO 26262 with tool confidence level 1. To accelerate SPICE simulation without sacrificing accuracy, state-of-the-art approaches have started to employ GPUs to parallelize the LU-factorization and device linearization phases. Instead of focusing on these phases, this work demonstrates for the first time that when large circuits come into play, a new and equally important performance bottleneck emerges at the circuit setup phase. Speeding up the circuit setup phase in SPICE is our key focus in this paper. Our two implementations demonstrate that our GPU-based circuit setup reduces the analysis time from 4.5 days to merely 89 seconds for a 256-bit multiplier, which consists of more than 1M transistors. Our achieved speedup is 4396x compared to the baseline (open-source NGSPICE) and more than 2x compared to commercial (HSPICE and Spectre) SPICE circuit setup.

SPICE model of a real capacitor : Capacitive feature analysis with voltage variation

Abstract: As it is known the passive components like the resistor, the coil and the capacitor in reality are not ideal components and have a nonlinear component. In this paper is started from the real equivalent circuit of a capacitor and is created a nonlinear SPICE model whose static capacity varies with voltage. The correctness of the SPICE model is studied on the capacitive region of the capacitor. Also, a study of the behavior of the SPICE model without considering the variation with temperature, aging, ESL and ESR will be presented. All to be considered in a future paper. The behavior of the SPICE model is compared with the behavior of the real capacitor and with the SPICE behavior of the capacitor proposed by the component manufacturer.

Modelling of phase‐shift modulated bidirectional CLLC resonant converter

Abstract: The study proposes the application of two modelling techniques for analysis of bidirectional CLLC resonant converters. The state-variable and cyclic-averaging techniques are applied for converters operating under two types of phase-shift modulation: single-phase-shift and pulse-phase modulation. The converter is analysed considering forward and reverse power flow directions and a state-variable equation description is obtained for both modes. The models are first validated through simulation, comparing the state-variable and cyclic-averaging results to a simulation program with integrated circuit emphasis (SPICE)-based simulation. Additionally, a low power prototype is built, experimental results are presented and the influence of parasitic elements and system delays is discussed. Simulation and experimental results show the models can accurately represent the behaviour of CLLC converters for both types of phase-shift modulation. In addition, using the cyclic-averaging technique results in a considerably faster execution compared to state-variable and SPICE-based models.

Application of the averaged model of the diode-transistor switch for modelling characteristics of a boost converter with an IGBT

Abstract: DC-DC converters are popular switch-mode electronic circuits used in power supply systems of many electronic devices. Designing such converters requires reliable computation methods and models of components contained in these converters, allowing for accurate and fast computations of their characteristics. In the paper, a new averaged model of a diode-transistor switch containing an IGBTis proposed. The form of the developed model is presented. Its accuracy is verified by comparing the computed characteristics of the boost converter with the characteristics computed in SPICE using a transient analysis and literature models of a diode and an IGBT. The obtained results of computations proved the usefulness of the proposed model.

Integrated circuit IBIS model extraction method and system based on equivalent circuit model

Abstract: The invention provides an integrated circuit IBIS model extraction method and system based on an equivalent circuit model, and the method comprises the steps: obtaining multilayer integrated circuit layout information of a passive part of an integrated circuit, and setting extraction related parameters and simulation parameters; identifying a parallel plate field domain formed by a metal layer-medium of the passive part of the multi-layer integrated circuit, performing mesh generation, and calculating an electromagnetic field; defining a multiport network of the passive part, calculating scattering parameters of the multiport network of the passive part according to multiports of the passive part and the electromagnetic field of the multilayer integrated circuit, and converting the scattering parameters into an SPICE model of the passive part; if the model is the active model, combining the SPICE model of the active part and the passive SPICE model into a new SPICE model through coupling nodes; and converting the SPICE model into an IBIS model. The IBIS model extraction related parameters and simulation parameters of the IC packaging network can be set according to different requirements of users, and the method has the advantages of being high in IBIS model extraction integrity, high in extraction efficiency, high in simulation accuracy and the like.