Showing papers on "Spice published in 2021"
TL;DR: A regularized minimization algorithm is presented, referred to as 1bSLIM, for accurate range-Doppler imaging using one-bit radar systems and two efficient implementations of the aforementioned algorithms are investigated that rely heavily on the use of FFTs.
Abstract: We consider the problem of range-Doppler imaging using one-bit automotive LFMCW1 or PMCW radar that utilizes one-bit ADC sampling with time-varying thresholds at the receiver. The one-bit sampling technique can significantly reduce the cost as well as the power consumption of automotive radar systems. We formulate the one-bit LFMCW/PMCW radar range-Doppler imaging problem as one-bit sparse parameter estimation. The recently proposed hyperparameter-free (and hence user friendly) weighted SPICE algorithms, including SPICE, LIKES, SLIM and IAA, achieve excellent parameter estimation performance for data sampled with high precision. However, these algorithms cannot be used directly for one-bit data. In this paper we first present a regularized minimization algorithm, referred to as 1bSLIM, for accurate range-Doppler imaging using one-bit radar systems. Then, we describe how to extend the SPICE, LIKES and IAA algorithms to the one-bit data case, and refer to these extensions as 1bSPICE, 1bLIKES and 1bIAA. These one-bit hyperparameter-free algorithms are unified within the one-bit weighted SPICE framework. Moreover, efficient implementations of the aforementioned algorithms are investigated that rely heavily on the use of FFTs. Finally, both simulated and experimental examples are provided to demonstrate the effectiveness of the proposed algorithms for range-Doppler imaging using one-bit automotive radar systems.
23 citations
TL;DR: A SPICE circuit able to predict dynamic core-losses in ferrite inductors with non-uniform magnetic field and the design of a circuit to ensure accurate power losses estimation even in presence of signals affected by noise is presented.
Abstract: This article presents a SPICE circuit that is able to predict dynamic core losses in ferrite inductors with nonuniform magnetic field. The circuit is supplied by a current generator and provides the core power loss as output. The article moves from models available in literature, which has been modified by the introduction of two main improvements allowing to extend the fields of applications. The first one is the design of a circuit that is able to ensure accurate power losses estimation even in the presence of signals affected by noise. The second improvement extends the usability of the model also to those cases where the magnetic material saturates because of high current or temperature effect. Extensive experimental tests to assess the accuracy of the estimations and simulations have been carried out.
19 citations
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TL;DR: SPICE as mentioned in this paper combines the discrepancy among semantic clusters, the similarity among instance samples, and the semantic consistency of local samples in an embedding space to optimize the clustering network in a semantically-driven paradigm.
Abstract: This paper presents SPICE, a Semantic Pseudo-labeling framework for Image ClustEring. Instead of using indirect loss functions required by the recently proposed methods, SPICE generates pseudo-labels via self-learning and directly uses the pseudo-label-based classification loss to train a deep clustering network. The basic idea of SPICE is to synergize the discrepancy among semantic clusters, the similarity among instance samples, and the semantic consistency of local samples in an embedding space to optimize the clustering network in a semantically-driven paradigm. Specifically, a semantic-similarity-based pseudo-labeling algorithm is first proposed to train a clustering network through unsupervised representation learning. Given the initial clustering results, a local semantic consistency principle is used to select a set of reliably labeled samples, and a semi-pseudo-labeling algorithm is adapted for performance boosting. Extensive experiments demonstrate that SPICE clearly outperforms the state-of-the-art methods on six common benchmark datasets including STL10, Cifar10, Cifar100-20, ImageNet-10, ImageNet-Dog, and Tiny-ImageNet. On average, our SPICE method improves the current best results by about 10% in terms of adjusted rand index, normalized mutual information, and clustering accuracy.
19 citations
TL;DR: A new realization of a grounded simulated inductor using a single dual output second-generation voltage conveyor (VCII±) as an active building block, two resistors and one grounded capacitor that has the property of improved low-frequency performance.
Abstract: This paper presents a new realization of a grounded simulated inductor using a single dual output second-generation voltage conveyor (VCII±) as an active building block, two resistors and one grounded capacitor. The main characteristic of the proposed circuit is that the value of the series resistor can be significantly reduced. Thus, it has the property of improved low-frequency performance. Another feature is the use of a grounded capacitor that makes the proposed circuit attractive for integrated circuit (IC) realization. A simple CMOS implementation of the required VCII± is used. However, a single passive component-matching condition is required for the proposed structure. As an application example, a standard fifth-order high-pass ladder filter is also given. SPICE simulations using 0.18 μm CMOS technology parameters and a supply voltage of ±0.9 V as well as experimental verifications, are carried out to support the theory.
17 citations
TL;DR: In this article, the use of FT-IR spectroscopy for the detection of adulteration in the cinnamon supply chain by several lower value ingredients was explored, and two species of cinnamon (C. verum and C. cassia) and an adulterant (cinnamon spend, n = 2) were used to create 110 different in-house admixtures.
Abstract: Cinnamon is a popular spice with a lengthy overseas supply chain. C. cassia is commonly traded as cinnamon, but the use of rapid methods to detect its adulteration has not yet been fully addressed. This work explores the use of FT-IR spectroscopy for the detection of adulteration in the cinnamon supply chain by several lower value ingredients. Two species of cinnamon (C. verum and C. cassia) and an adulterant (cinnamon spend, n = 2) were used to create 110 different in-house admixtures. Two different replacement fraud experiments were designed: C. cassia replaced with spend (Scenario A) and C. verum replaced with both C. cassia and spend (Scenario B). Initial analysis by GC-IMS showed promising differences between samples. The FT-IR spectra confirmed significant raw differences in absorbance. PCA for Scenario A demonstrated better separation than in Scenario B. The detection of adulteration of C. cassia (Scenario A) and C. verum (Scenario B) were equality accurate. Classification results showed that the PLS-DA technique was superior to SIMCA for both types of adulteration (PLS-DA: 94-90%; SIMCA: 83-79%, respectively). This demonstrates the potential of FT-IR as a screening method to identify cinnamon adulteration in supply chains and to provide accurate and rapid results without sample preparation.
17 citations
TL;DR: The LTSpice circuit simulation shows the same characteristics as the original MATLAB numerical implementation, which means that the circuit-level SPICE model can be integrated with other designs and proves that the behavioral memristor model has potential application in digital system design.
Abstract: In this paper, a behavioral SPICE memristor model for digital logic implementation is presented and demonstrated in LTSpice. We show binarized state switching and voltage thresholding in the model, which are both important features in practical digital systems. The use of this SPICE model is straightforward and intuitive because almost all parameters in the model can be changed according to the application, including the threshold voltage and the memristance. The LTSpice circuit simulation shows the same characteristics as the original MATLAB numerical implementation, which means that the circuit-level SPICE model can be integrated with other designs. Three types of memristor digital logic circuits are simulated with the LTSpice model with positive results, which proves that the behavioral memristor model has potential application in digital system design.
16 citations
TL;DR: A set of models of memristive devices for a reliable, accurate and fast analysis of large networks in the SPICE environment are introduced that utilize the synergy of several techniques such as window asymmetrization, integration with saturation, state equation preprocessing, scaling, and smoothing.
Abstract: The paper introduces a set of models of memristive devices for a reliable, accurate and fast analysis of large networks in the SPICE (Simulation Program with Integrated Circuit Emphasis) environment. The modeling starts from the recently introduced TEAM (ThrEshold Adaptive Memristor Model) and VTEAM (Voltage ThrEshold Adaptive Memristor Model). A number of improvements are made towards the stick effect elimination and other numerical refinements to make the analysis of large networks fast and accurate. A set of models are proposed that utilize the synergy of several techniques such as window asymmetrization, integration with saturation, state equation preprocessing, scaling, and smoothing. The performance of models is tested in Cadence PSPICE 17.2 and particularly in HSPICE v2017, the latter on a large-scale CNN (Cellular Nonlinear Network) for detecting edges of binary images. The simulations manifest the usability of developed models for fast and reliable operation in networks containing more than one million nodes.
11 citations
TL;DR: This paper shows that GaN-HEMTs can be modeled by selected equations from the standard MOSFET LEVEL 3 model in SPICE and a method is proposed for the extraction of SPICE parameters in these equations.
Abstract: The device library in the standard circuit simulator (SPICE) lacks a gallium nitride based high-electron-mobility-transistor (GaN-HEMT) model, required for the design and verification of power-electronic circuits. This paper shows that GaN-HEMTs can be modeled by selected equations from the standard MOSFET LEVEL 3 model in SPICE. A method is proposed for the extraction of SPICE parameters in these equations. The selected equations and the proposed parameter-extraction method are verified with measured static and dynamic characteristics of commercial GaN-HEMTs. Furthermore, a double pulse test is performed in LTSpice and compared to its manufacturer model to demonstrate the effectiveness of the MOSFET LEVEL 3 model. The advantage of the proposed approach to use the MOSFET LEVEL 3 model, in comparison to the alternative behavioral-based model provided by some manufacturers, is that users can apply the proposed method to adjust the parameters of the MOSFET LEVEL 3 model for the case of manufacturers who do not provide SPICE models for their HEMTs.
10 citations
TL;DR: A TCM based on multigradient neural network (MNN) using computational graph in the PyTorch framework is developed, which enables more precise circuit simulation for analog and RF circuits, and provides a rapid solution for early stage design technology cooptimization (DTCO).
Abstract: Transistor compact model (TCM) is the key bridge between process technology and circuit design. Typically, TCM is desired to capture the nonlinear device electronic characteristics and their high-order derivatives. However, for the novel devices in advanced and future technologies, establishing TCM based on analytical equations and extracting model parameters becomes tedious. The model fitting capability for device outputs’ high-order derivatives is also limited. These drawbacks hinder fast and accurate device to circuit evaluation cycles. We develop a TCM based on multigradient neural network (MNN) using computational graph in the PyTorch framework. This MNN model is able to simultaneously capture the transistor dc/ac characteristics, such as ${I}-{V}/{Q}-{V}$ , their derivatives ( ${G}-{V}/{C}-{V}$ ), and higher order derivatives accurately. Moreover, the model architecture can be widely adapted to various device types. Based on this model scheme, software is developed to enable the automated model generation for standard SPICE simulation. Finally, the model and software are validated for novel gate-all-around (GAA) Si cold source field-effect transistors (CSFET), and 19-stage ring oscillator and two-stage operational amplifier circuit simulations have also been demonstrated. This work reduces the cycle of novel device compact model creation and circuit benchmark simulation from months or weeks to hours. In addition, it enables more precise circuit simulation for analog and RF circuits, and it provides a rapid solution for early stage design technology cooptimization (DTCO).
9 citations
TL;DR: A systematic comparison of the five circuit topologies for thin-film transistor (TFT) based digital inverter (NOT gate) is presented, exploiting the measured characteristics of a high-performance organic TFT, widely adopted unipolar and complementary inverter circuits are simulated in SPICE.
7 citations
TL;DR: This article presents a scheme to independently control the outputs of an MOFC, thereby achieving an excellent cross-regulation performance over a wide range of loads, without any additional switching or magnetic component.
Abstract: Several techniques are proposed in the literature to improve the cross-regulation performance of a multiple output flyback converter (MOFC). However, some drawbacks exist: 1) inability to completely eliminate cross-regulation, 2) reduction of power density due to a high number of additional components, 3) increased losses. To overcome these challenges, this paper presents a scheme to independently control the outputs of an MOFC, thereby achieving excellent cross-regulation performance over a wide range of loads, without any additional switching or magnetic component. The unique gate dependent reverse conduction characteristics of gallium nitride (GaN) high electron mobility transistor (HEMT) is utilized to control the flow of current to each of the output capacitors. The operational principle and the steady-state analysis is provided in detail. Moreover, design considerations such as the switching frequency, GaN gate bias, leakage inductances, output capacitance etc. are discussed, focusing on their impacts on the key design goals, particularly the efficiency, power density, and output voltage ripple. Furthermore, SPICE simulations are used to demonstrate the improvement in cross-regulation over existing schemes. Finally, a 40 W dual output laboratory prototype is built to verify the analysis. The measured maximum cross-regulation is 0.2% which validates the effectiveness of the scheme.
TL;DR: Simulations using the validated multisegment simulation program with integrated circuit emphasis (SPICE) model show that the terahertz spectrometers using plasmonic field effect transistors could be used for the frequency to digital conversion.
Abstract: Our simulations using the validated multisegment simulation program with integrated circuit emphasis (SPICE) model show that the terahertz (THz) spectrometers using plasmonic field effect transistors could be used for the frequency to digital conversion. The THz SPICE unified charge control model that uses the distributed channel resistances, capacitances, and Drude inductances is validated by technology computer-aided design simulations. The THz spectrometers using Si plasmonic field effect transistors (or TeraFETs) determine the frequency of the impinging radiation by measuring the gate bias where the responsivity changes sign. This crossover frequency is sensitive to the channel length and nearly insensitive to the gate bias in the weak and moderate inversion regions. This unique feature allows the use of multiple THz spectrometers with different channel lengths to implement the frequency-to-digital converters in the sub-THz and THz frequency range. The simulations predict the operation frequency from 110 GHz up to 4 THz for the frequency-to-digital converters using Si TeraFETs with feature sizes from 20 to 130 nm.
TL;DR: This is the first attempt to implement transimpedance type filters with MOS-only technique and the resulting circuits will be a useful solution for many applications where the available signal is current and the necessary signal for further processing is voltage type.
Abstract: In this paper, we present six area-efficient transimpedance type second-order analog filters. There are many applications where the available signal is current, however the necessary signal for further processing is voltage type.
For such applications the presented circuits will be a useful solution. The technique employed is called MOS-only technique and to the best of our knowledge this is the first attempt to implement transimpedance type filters with MOS-only technique. Starting from the core circuit biasing is illustrated and the functionality is shown with LT SPICE simulations using TSMC 0.18u technology parameters. From six core circuits one circuit is selected and the design is completed for illustration purpose.
TL;DR: In this article, a SPICE model for multi-domain switching dynamics for a metal-ferroelectric-insulator-semiconductor (MFIS) type negative capacitance Fin Field Effect Transistor (NC-FinFET) was proposed.
TL;DR: In this article, a charge-based analytic and explicit compact model for field effect transistors (FETs) based on 2D materials (2DMs), for the simulation of 2DM-based analog and digital circuits is presented.
Abstract: We report a charge-based analytic and explicit compact model for field-effect transistors (FETs) based on 2-D materials (2DMs), for the simulation of 2DM-based analog and digital circuits. The device electrostatics is handled by invoking 2-D density of states and Fermi–Dirac statistics that are later combined with the Lambert-W function and Halley’s correction to eventually obtain explicit expressions for the electron and hole charges, which are exploited in the calculation of drift-diffusion currents for both carriers. Furthermore, the charge model is extended to obtain characteristics of 2DM-based negative capacitance FETs. The model is benchmarked against experimental MoS2 FET measurements and experimental ambipolar characteristics of narrowband-gap materials, such as black phosphorus. Its soundness for SPICE circuit-level simulations is also demonstrated.
13 Oct 2021
TL;DR: In this paper, the primary inductor current of a coupled wireless power transfer (WPT) system was analyzed for cases such as off-resonant operation, overtuned-and undertuned-capacitor operation, and effects due to finite rise and fall times.
Abstract: Class-D half-bridge power amplifiers (PA) are used to drive the primary coil of a coupled wireless power transfer (WPT) system. We analyze the primary inductor current of cases such as off-resonant operation, overtuned- and undertuned-capacitor operation, and effects due to finite rise and fall times. We also analyze the case with off-resonant Zero Voltage Switching (ZVS) tank. SPICE simulations validate all the analytical calculations with errors smaller than 2%.
TL;DR: In this article, a SPICE compatible compact modeling of indium gallium zinc oxide (IGZO)-based flexible electronics is presented for reliability-aware simulation in both device and circuit levels.
Abstract: Accurate circuit simulation reflecting physical and electrical stress is of importance in indium gallium zinc oxide (IGZO)-based flexible electronics. In particular, appropriate modeling of threshold voltage (VT) changes in different bias and bending conditions is required for reliability-aware simulation in both device and circuit levels. Here, we present SPICE compatible compact modeling of IGZO transistors and inverters having an atomic layer deposition (ALD) Al2O3 gate insulator on a polyethylene terephthalate (PET) substrate. Specifically, the modeling was performed to predict the behavior of the circuit using stretched exponential function (SEF) in a bending radius of 10 mm and operating voltages ranging between 4 and 8 V. The simulation results of the IGZO circuits matched well with the measured values in various operating conditions. It is expected that the proposed method can be applied to process improvement or circuit design by predicting the direct current (DC) and alternating current (AC) responses of flexible IGZO circuits.
TL;DR: In this article, a closed form expression was used to obtain the values of the five parameters of the one diode model by developing closed form expressions and the maximum error produced by this technique is 10% when compared to the exact values of a one-diode model circuit built by Spice, however, even for this same parameter the model outperforms many iterative dependent works.
Abstract: With the wide acceptance of modeling a PV cell by a single diode, a series and parallel resistors; many researchers have discussed different mathematical forms and iterative techniques to extract the values of these model elements depending on the key parameters provided by the manufacturer datasheet. This paper avoids iterative techniques and obtains the values of the five parameters of the one diode model by developing closed form expressions. The maximum error produced by this technique is 10% when compared to the exact values of the one diode model circuit built by Spice. The 10% maximum error has occurred during the estimation of the reverse saturation current (Io) of the diode, nevertheless, it should be mentioned that even for this same parameter the model outperforms many iterative dependent works. Furthermore, this paper discusses the effect of temperature on the operation performance of PV cells. In particular, the temperature effect on the open circuit voltage, the short circuit current, the fill factor, the reverse saturation current, and the conversion efficiency was modeled and evaluated for different brand technologies
TL;DR: In this article, a hybrid finite-difference time-domain-simulation program with integrated circuit emphasis (FDTD-SPICE) method was proposed to analyze the system-level coupling responses of the wireless communication system with antenna, metallic enclosures, braided shielded cable, and lumped element, when illuminated by an external electromagnetic pulse.
Abstract: This article presents a hybrid finite-difference time-domain–simulation program with integrated circuit emphasis (FDTD–SPICE) method for analyzing the system-level coupling responses of the wireless communication system with antenna, metallic enclosures, braided shielded cable, and lumped element, when illuminated by an external electromagnetic pulse (EMP). In the hybrid method, a system-level SPICE model combining antenna and braided coaxial cable is proposed to predict the coupling effects including front-door and back-door couplings. FDTD is used to calculate the induced current on the outer conductor of the coaxial cable, which is then incorporated into the system-level SPICE model as an additional current source. Because the hybrid method avoids meshing the antenna and cable, it has higher computational efficiency than full-wave analysis. A typical microstrip antenna system is selected as a case to demonstrate the accuracy and effectiveness of this proposed method by comparing the numerical results with those obtained by CST. Then, considering the influence of the incident conditions of external EMP, the coupling voltages of the microstrip antenna system are calculated. Furthermore, a typical filter circuit is analyzed to illustrate the practicability of the proposed method. The obtained coupling response information demonstrate that the proposed method is available for designing electromagnetic protection of the inner circuits of the wireless communication system against the impact of external incident wave.
06 Oct 2021
TL;DR: In this article, the authors demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used.
Abstract: In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local slew errors at cutpoints, and secondly because slew propagation may not be upper bounded across multiple cut points in the same cycle. The use of an Asynchronous STA (ASTA) engine, which does not cut cycles, and properly bounds slews across cycles is a possible solution, which can indeed serve as an upper bound over SPICE transistor level similations. We contrast STA and ASTA-based gate-level simulations with transistor level SPICE simulations to demonstrate the impact of timing errors for 12 asynchronous control circuits, implemented by the Petrify tool, in a 0.25μm technology library. We show that STA-based simulation results are incorrectly more optimistic than ASTA, and it is possible for the simulation period to even be faster than SPICE, which is a major timing error.
TL;DR: A novel modified piece-wise linear (PWL) window function proposed for the nonlinear property of the memristor SPICE model to address the shortcoming of the parabola and Heaviside- step function based typical window functions proposed in the literature.
TL;DR: A total gate area reduction of approximately 30% of a robust OTA implemented with Diamond MOSFETs is revealed, with an alpha angle equal to 45°, with respect to the one observed in the robust Ota implemented with standard MOSfETs, maintaining practically the same electrical performance and robustness.
Abstract: This paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The Single-Ended Single-Stage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named iMTGSPICE, was used to design and optimize the SESS OTA. There are several heuristics optimization techniques of Artificial Intelligence to optimize analog and radio-frequency CMOS ICs, but we have selected to use the Genetic Algorithm because it presents the best optimization performance among the other algorithms previously studied. This paper also describes a procedure of converting the Conventional planar MOSFETs (rectangular gate shape) into the Diamond MOSFETs (hexagonal gate shape) with the same electrical performance. Furthermore, it is proposed a procedure to simulate the Diamond MOSFETs (DMs) in the Simulation Program with Integrated Circuit Emphasis (SPICE) because there is still no SPICE model to perform the DM. Additionally, this work proposes a methodology to layout OTAs with Diamond MOSFETs, regarding different values of aspect ratios. The main result of this work reveals a total gate area reduction of approximately 30% of a robust OTA implemented with Diamond MOSFETs, with an alpha angle (α) equal to 45°, with respect to the one observed in the robust OTA implemented with standard MOSFETs, maintaining practically the same electrical performance and robustness.
24 Feb 2021
TL;DR: In this paper, a read access yield estimation method for high-density static random access memory (SRAM) is proposed, where instead of performing SPICE runs for the entire SRAM circuit, the proposed method partitions the SRAM into three parts, the control signal generation circuit, bitcell array, and sense amplifier (SA), that determine three key parameters: word-line to SA enable delay, bit-line voltage difference, and SA offset voltage.
Abstract: As high-density SRAMs must be designed to ensure a substantially small failure rate, the accurate yield estimation with practically acceptable runtime of circuit simulations is highly challenging. Here, a read access yield estimation method for high-density static random access memory (SRAM) is proposed. Instead of performing SPICE runs for the entire SRAM circuit, the proposed method partitions the SRAM into three parts—the control signal generation circuit, bitcell array, and sense amplifier (SA)—that determine three key parameters: word-line to SA enable delay, bit-line voltage difference, and SA offset voltage. Subsequently, the proposed method derives the probability density of these key parameters from each of the three partitioned circuits. Here, different methods are applied to derive the probability of the key parameters, considering the respective characteristics of each circuit part and parameter. According to our experimental results, the proposed method can accelerate the yield estimation by 500– $3000\times $ , compared with the brute-force Monte Carlo simulation method, and 10– $100\times $ compared with the other state-of-art methods. In addition, the proposed method can accelerate the circuit optimization procedure accompanied by multiple circuit revisions, that is, the circuit revisions can be reflected with SPICE runs only for the revised circuit part, unlike the previous methods that require SPICE runs for the entire SRAM.
TL;DR: In this article, a generic and simple emulator circuit for a voltage controlled memristor is presented using a differential difference current conveyor transconductance amplifier (DDCCTA), which is based on a versatile second-generation current conveying methodology.
TL;DR: In this article, the authors revisited the mathematical formulation to compensate for some ambiguities in the original manuscript, and pointed out some inconsistencies in the results and reproducibility of the simulations, as well as in the optimized parameters originally obtained with the PSPICE simulation engine.
Abstract: The paper “SPICE Model of Photomultiplier Tube Under Different Bias Conditions” is commented. We revisit the mathematical formulation to compensate for some ambiguities in the original manuscript, and point out some inconsistencies in the results and reproducibility of the simulations, as well as in the optimized parameters originally obtained with the PSPICE simulation engine. All simulations are recalculated with the NGSPICE software using the corrected parameters and compared against the original figures. The reproducibility of our simulations is independently verified with PSPICE, as well as by numerically solving the analytical system of non-linear equations using Newton’s method within MATLAB.