Spice

About: Spice is a research topic. Over the lifetime, 3966 publications have been published within this topic receiving 40204 citations. The topic is also known as: spices.

MOSFET Models for SPICE Simulation: Including BSIM3v3 and BSIM4

Abstract: Preface. 1 Modeling Jargons. 1.1 SPICE Simulator and SPICE Model. 1.2 Numerical Iteration and Convergence. 1.3 Digital vs. Analog Models. 1.4 Smoothing Function and Single Equation. 1.5 Chain Rule. 1.6 Quasi-Static Approximation. 1.7 Terminal Charges and Charge Partition. 1.8 Charge Conservation. 1.9 Non-Quasi-Static and Quasi-Static y-Parameters. 1.10 Source-Referencing and Inverse Modeling. 1.11 Physical Model and Table-Lookup Model. 1.12 Scalable Model and Device Binning. References and Notes. 2 Basic Facts About BSIM3. 2.1 What Is and What's Not Implemented in BSIM3. 2.2 DC Equivalent Circuit Model. 2.3 BSIM3's ^-Parameters. 2.4 Large-Signal Equivalent Circuit. 2.5 Small-Signal Model. 2.6 Noise Equivalent Circuit. 2.7 Special Operating Conditions: VDS 0, VGS 0> . References and Notes. 3 BSIM3 Parameters. 3.1 List of Parameters According to Function. 3.2 Alphabetical Glossary of BSIM3 Parameters. 3.3 Flow Diagram of SPICE Simulation. References and Notes. 4 Improvable Areas of BSIM3. 4.1 Lack of Robust Non-Quasi-Static Models: Transient Analysis. 4.2 Problem with the 40/60 Partition: The "Killer NOR Gate". 4.3 Lack of Channel Resistance (NQS Effect Small-Signal Analysis). 4.4 Incorrect Transconductance Dependency on Frequency. 4.5 Lack of Gate Resistance (and Associated Noise). 4.6 Lack of Substrate Distributed Resistance (and Associated Noise). 4.7 Incorrect Source/Drain Asymmetry at VDS = 0. 4.8 Incorrect Cgb Behaviors. 4.9 Capacitances with Wrong Signs. 4.10 Cgg Fit and Other Capacitance Issues. 4.11 Insufficient Noise Modeling (No Excess Short-Channel Thermal Noise). 4.12 Insufficient Noise Modeling (No Channel-Induced Gate Noise). 4.13 Incorrect Noise Figure Behavior. 4.14 Inconsistent Input-Referred Noise Behavior. 4.15 Possible Negative Transconductances. 4.16 Lack of GIDL (Gate-Induced Drain Leakage) Current. 4.17 Incorrect Subthreshold Behaviors. 4.18 Threshold Voltage Rollup. 4.19 Problems Associated with a Nonzero RDSW. 4.20 Other Nuisances. References and Notes. 5. Improvements in BSIM4. 5.1 Introduction. 5.2 Physical and Electrical Oxide Thicknesses. 5.3 Strong Inversion Potential for Vertical Nonuniform Doping Profile. 5.4 Threshold Voltage Modifications. 5.5 VGST^ in Moderate Inversion. 5.6 Drain Conductance Model. 5.7 Mobility Model. 5.8 Diode Capacitance. 5.9 Diode Breakdown. 5.10 GIDL (Gate-Induced Drain Leakage) Current. 5.11 Bias-Dependent Drain-Source Resistance. 5.12 Gate Resistance. 5.13 Substrate Resistance. 5.14 Overlap Capacitance. 5.15 Thermal Noise Models. 5.16 Flicker Noise Model. 5.17 Non-Quasi-Static AC Model. 5.18 Gate Tunneling Currents. 5.19 Layout-Dependent Parasitics. References and Notes. Appendixes. A BSIM3 Equations. B Capacitances and Charges for All Bias Conditions. C Non-Quasi-Static ^-Parameters. D Fringing Capacitance. E BSIM3 Non-Quasi-Static Modeling. F Noise Figure. G BSIM4 Equations. Index.

MOS transistor modeling for RF IC design

Abstract: This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-/spl mu/m CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement.

A behavioral macromodel of the ISFET in SPICE

Abstract: Physico-chemical models of the ISFET (Ion-Sensitive Field-Effect Transistor) were developed by the authors in the past, as SPICE built-in models (BIOSPICE). This approach has some drawbacks, i.e., the need of availability of the program source, a deep knowledge of the code subroutines and structure, and the need of compiling the whole program when a new model has to be implemented or when modifications to the models have to be made. To overcome these drawbacks, a more general and user-friendly approach is presented. It consists of a behavioral macromodel that can be used in conjunction with the most commercial SPICE versions. The behavior of the proposed macromodel has been validated by comparing the results with those obtained by BIOSPICE physico-chemical models and experimental measurements. The proposed macromodel is shown to operate also under subthreshold conditions that can be considered as a promising operating mode for large multisensor ISFET-based integrated systems.

A Memristor SPICE Implementation and a New Approach for Magnetic Flux-Controlled Memristor Modeling

Abstract: This paper introduces a behavior model of a memristive soild-state device for simulation with a simulation program for integrated circuits emphasis (SPICE) compatible circuit simulator. After showing the underlying functional mechanics and model equations of a memristor the SPICE equivalent circuit based on a charge controlled memristor is presented and discussed. Hereafter, a magnetic flux controlled memristor model is introduced including technical description and SPICE implementation. It is shown that the presented SPICE models meet the requirements for simulations of multi memristor circuits.