Showing papers on "Split-radix FFT algorithm published in 1975"
TL;DR: New and accurate models can be derived to model quantization errors in high-speed convolution filters by analyzing two forms of FFT quantization, coefficient rounding and floating point arithmetic quantization.
Abstract: When a fast Fourier transform (FFT) is implemented on a digital machine, quantization errors will arise due to finite word lengths in the digital system. The magnitudes and characteristics of these errors must be known if an FFT is to be designed with the minimum word lengths needed for acceptable performance. Two forms of FFT quantization, coefficient rounding and floating point arithmetic quantization, are analyzed in this paper. A theory is presented from which several new results can be obtained. The error characteristics of FFT's using exact and truncated values for the coefficients 1 and -j are found to be roughly equivalent. The accuracy of the theory is tested by computer simulations. Using the models introduced in this paper, new and accurate models can be derived to model quantization errors in high-speed convolution filters.
40 citations
TL;DR: The organization and functional design of a parallel radix-4 fast Fourier transform (FFT) computer for real-time signal processing of wide-band signals is introduced.
Abstract: The organization and functional design of a parallel radix-4 fast Fourier transform (FFT) computer for real-time signal processing of wide-band signals is introduced.
22 citations
Patent•
03 Mar 1975TL;DR: In this paper, two kinds of apparatus for combining N 2 chirp-Z transform (CZT) modu of length n 1 to perform a discrete Fourier transform (DFT) of length N 1 N 2.
Abstract: Two kinds of apparatus for combining N 2 chirp-Z transform (CZT) modu of length N 1 to perform a discrete Fourier transform (DFT) of length N 1 N 2 . The first method uses an auxiliary parallel-input, parallel-output, DFT device of size N 2 and allows the transform of size N 1 N 2 to be performed in the same time as is required for a single CZT module to perform a size N 1 transform. The second method uses an auxiliary parallel-input, serial-output, DFT device of size N 2 . If the second method is implemented entirely in a single technology, such as with charge-coupled devices (CCDs), it performs the size N 1 N 2 transform in N 2 times the amount of time required for a single CZT module to perform a size N 1 transform. If N 2 is a composite number, say N 2 = M 1 M 2 , the second method also permits the same hardware to perform M 1 simultaneous transforms of length N 1 M 2 .
10 citations
TL;DR: A new algorithm is described in detail (including a flowdiagram) which provides savings of core storage and execution time of a factor of four as compared to the standard FFT algorithm.
8 citations