Showing papers on "Split-radix FFT algorithm published in 2011"

On the stability of the hyperbolic cross discrete Fourier transform

Abstract: A straightforward discretisation of problems in high dimensions often leads to an exponential growth in the number of degrees of freedom. Sparse grid approximations allow for a severe decrease in the number of used Fourier coefficients to represent functions with bounded mixed derivatives and the fast Fourier transform (FFT) has been adapted to this thin discretisation. We show that this so called hyperbolic cross FFT suffers from an increase of its condition number for both increasing refinement and increasing spatial dimension.

Fast Walsh–Hadamard–Fourier Transform Algorithm

Abstract: An efficient fast Walsh-Hadamard-Fourier transform algorithm which combines the calculation of the Walsh-Hadamard transform (WHT) and the discrete Fourier transform (DFT) is introduced. This can be used in Walsh-Hadamard precoded orthogonal frequency division multiplexing systems (WHT-OFDM) to increase speed and reduce the implementation cost. The algorithm is developed through the sparse matrices factorization method using the Kronecker product technique, and implemented in an integrated butterfly structure. The proposed algorithm has significantly lower arithmetic complexity, shorter delays and simpler indexing schemes than existing algorithms based on the concatenation of the WHT and FFT, and saves about 70%-36% in computer run-time for transform lengths of 16-4096.

A pipelined architecture for normal I/O order FFT

Abstract: We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order A single-path delay commutator processing element (SDC PE) has been proposed for the first time It saves a complex adder compared with the typical radix-2 butterfly unit The new pipelined architecture can be built using the proposed processing element The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage

On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems

Abstract: This paper treats the hardware architecture and implementation of mixed radix FFTs with cores of radix 3 and radix 5 in addition to the standard radix 2 core. The implementation flow graphs of the higher radix cores are presented together with a description of how these cores affect a pipelined FFT implementation. It is shown that the mixed radix FFT is more expensive than the radix 2 implementation - a mixed radix FFT of 1200 points require 36 real multipliers in a pipelined implementation whereas a 2048 radix 2 FFT needs 30 real multipliers. However, half of the multipliers in the mixed radix case can be constant. Therefore it is still feasible to use the mixed radix FFT if an algorithm calls for it.

Generation of all radix-2 fast Fourier transform algorithms using binary trees

Abstract: In this work a systematic method to generate all possible fast Fourier transform (FFT) algorithms is proposed based on the relation to binary trees. The binary tree is used to represent the decomposition of a discrete Fourier transform (DFT) into sub-DFTs. The radix is adaptively changed according to compute sub-DFTs in proposed decomposition. In this work we determine the number of possible algorithms for 2n-point FFTs with radix-2 butterfly operation and propose a simple method to determine the twiddle factor indices for each algorithm based on the binary tree representation.

Analysis and optimization of PMF-FFT acquisition algorithm for high-dynamic GPS signal

Abstract: (Partial Matching Filter)PMF-(Fast Fourier Transformation)FFT algorithm has advantages in acquisition speed and hardware complexity. However in Doppler frequency acquisition there is a contradiction between acquisition accuracy and hardware complexity. In addition the range of frequency acquisition is limited. What's worse in this limited and small range, the peak of output seriously decline with the increasing of Doppler frequency. To solve problems above, first of all this paper analyzed the source of defects, accordingly FFT was replaced by (Discrete Fourier Transformation) DFT to eliminate the contradiction between acquisition accuracy and hardware complexity. Then this paper used the known Doppler frequency got before losing track to switch the acquisition target from Doppler frequency itself to its variation during a shot time through which way the negative effects from limited acquisition range is avoided. Last this paper used a digital divider to dynamically eliminate the factor for attenuation of output peak. Theoretical analysis and simulation result showed that while keep the advantages of PMF-FFT algorithm the optimized algorithm had effectively overcame the defects sothat it will serve well in the design of receiver for high-dynamic GPS signal.

High speed eight-parallel mixed-radix FFT Processor for OFDM systems

Abstract: This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a higher throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. Using the modified radix-4 butterfly unit which can perform one radix-4 butterfly or two radix-2 butterflies, the proposed FFT processor can provide 128 and 256-point FFT computations. The proposed FFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

Sampling Rate Conversion in the Frequency Domain [DSP Tips and Tricks]

Abstract: Sampling rate conversion (SRC) is usually performed in the time domain by using the operations of up-sampling, filtering, and down-sampling. However, it is also possible to perform the SRC in the frequency domain by formulating the desired spectrum from the spectrum of an input signal. This article shows how to perform SRC for both integer and fractional-rate conversion by manipulating the discrete Fourier transform (DFT), implemented using the fast Fourier transform (FFT), of a time-domain signal. The analysis on error performance and the required computational complexities show that by using the FFT, for both short and long input sequences, improvements in conversion accuracy is achieved at reduced computational costs.

Implementation techniques of high-order FFT into low-cost FPGA

Abstract: In this paper, our objective is to detail know-how and techniques that can help the designer of electronic circuits to develop and to optimize their own IP in a reasonable time. For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms. Indeed, we can obtain a VLSI structure by using log 4 (N) 4-point FFTs to construct N-point FFT rather than (N/8) log 8 (N) 8-point FFTs. Furthermore, two techniques are used to yield with VLSI architecture. Firstly, the radix-4 FFT is modified to process one sample per clock cycle. Secondly, the memory is shared and divided into 4 parts to reduce the consumed resources and to improve the overall latency. Comparisons with commercial IP cores show that the low area architecture presents the best compromise in terms of speed/area.

Spectrum analysis of speech recognition via discrete tchebichef transform

Abstract: Speech recognition is still a growing field It carries strong potential in the near future as computing power grows Spectrum analysis is an elementary operation in speech recognition Fast Fourier Transform (FFT) is the traditional technique to analyze frequency spectrum of the signal in speech recognition Speech recognition operation requires heavy computation due to large samples per window In addition, FFT consists of complex field computing This paper proposes an approach based on discrete orthonormal Tchebichef polynomials to analyze a vowel and a consonant in spectral frequency for speech recognition The Discrete Tchebichef Transform (DTT) is used instead of popular FFT The preliminary experimental results show that DTT has the potential to be a simpler and faster transformation for speech recognition

Truncated multigrid versus pre-corrected FFT/AIM for bioelectromagnetics: When is O(N) better than O(NlogN)?

Abstract: The effectiveness of multigrid and fast Fourier transform (FFT) based methods are investigated for accelerating the solution of volume integral equations encountered in bioelectromagnetics (BIOEM) analysis. The typical BIOEM simulation is in the mixed-frequency regime of analysis because the field variations in the simulation domain are dictated by a combination of the free space wavelength, geometrical features, and the wavelengths/skin depths in tissues. In this case, multigrid-based methods (when appropriately truncated at high-frequency levels) can achieve O(N) complexity that is asymptotically superior to the O(NlogN) complexity of FFT-based ones. Nevertheless, the constant in front of their asymptotic complexity estimate is larger and their accuracy-efficiency tradeoffs are different. Numerical experiments are performed to compare these methods and the results show that multigrid-based methods begin to outperform FFT-based ones for N∼103.

The Centered Discrete Fourier Transform and a parallel implementation of the FFT

Abstract: This paper describes a novel method for the computation of the Discrete Fourier Transform (DFT). The development of a truly centered DFT is coupled with a method for computing the Centered DFT to provide an FFT that requires no complex multiplications and which allows a highly parallel implementation.

VHDL implementation of an optimized 8-point FFT/IFFT processor in pipeline architecture for OFDM systems

Abstract: The Fast Fourier Transform (FFT) and its inverse transform (IFFT) processor are key components in many communication systems. An optimized implementation of the 8-point FFT processor with radix-2 algorithm in R2MDC architecture is presented in this paper. The butterfly — Processing Element (PE) used in the 8-FFT processor reduces the multiplicative complexity by using a real constant multiplication in one method and eliminates the multiplicative complexity by using add and shift operations in other proposed method. The pipeline architecture R2MDC has been implemented with the 8-point module and simulation results show that this module significantly achieves a better performance with lower resource usage.

Image Compression Based on Improved FFT Algorithm

Abstract: Image compression is a crucial step in image processing area. Image Fourier transforms is the classical algorithm which can convert image from spatial domain to frequency domain. Because of its good concentrative property with transform energy, Fourier transform has been widely applied in image coding, image segmentation, image reconstruction. This paper adopts Radix-4 Fast Fourier transform (Radix-4 FFT) to realize the limit distortion for image coding, and to discuss the feasibility and the advantage of Fourier transform for image compression. It aims to deal with the existing complex and time-consuming of Fourier transform, according to the symmetric conjugate of the image by Fourier transform to reduce data storage and computing complexity. Using Radix-4 FFT can also reduce algorithm time-consuming, it designs three different compression requirements of non-uniform quantification tables for different demands of image quality and compression ratio. Take the standard image Lena as experimental data using the presented method, the results show that the implementation by Radix-4 FFT is simple, the effect is ideal and lower time-consuming.

On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers

Abstract: Fixed-point Fast Fourier Transform (FFT) units are widely used in digital communication systems. The twiddle multipliers required for realizing large FFTs are typically implemented with the Coordinate Rotation Digital Computer (CORDIC) algorithm to restrict memory requirements. Recent approaches aiming to optimize the bit-widths of FFT units while satisfying a given maximum bound on Mean-Square-Error (MSE) mostly focus on the architectures with integer multipliers. They ignore the quantization error of coefficients, disabling them to analyze the exact error defined as the difference between the fixed-point circuit and the reference floating-point model. This paper presents an efficient analysis of MSE as well as an optimization algorithm for CORDIC-based FFT units, which is applicable to other Linear-Time-Invariant (LTI) circuits as well.

Spline-Interpolation-Based FFT Approach to Fast Simulation of Multivariate Stochastic Processes

Abstract: The spline-interpolation-based fast Fourier transform (FFT) algorithm, designated as the SFFT algorithm, is proposed in the present paper to further enhance the computational speed of simulating the multivariate stochastic processes. The proposed SFFT algorithm first introduces the spline interpolation technique to reduce the number of the Cholesky decomposition of a spectral density matrix and subsequently uses the FFT algorithm to further enhance the computational speed. In order to highlight the superiority of the SFFT algorithm, the simulations of the multivariate stationary longitudinal wind velocity fluctuations have been carried out, respectively, with resorting to the SFFT-based and FFT-based spectral representation SR methods, taking into consideration that the elements of cross-power spectral density matrix are the complex values. The numerical simulation results show that though introducing the spline interpolation approximation in decomposing the cross-power spectral density matrix, the SFFT algorithm can achieve the results without a loss of precision with reference to the FFT algorithm. In comparison with the FFT algorithm, the SFFT algorithm provides much higher computational efficiency. Likewise, the superiority of the SFFT algorithm is becoming more remarkable with the dividing number of frequency, the number of samples, and the time length of samples going up.

A higher radix FFT FPGA implementation suitable for OFDM systems

Abstract: This article describes a new approach for higher radix butterflies suitable for pipeline implementation. Based on the butterfly computation introduced by Cooley-Tukey [1], we will introduce a novel approach for the Discrete Fourier Transform (DFT) factorization, by redefining the butterfly computation, which is more suitable for efficient VLSI implementation. The proposed factorization motivated us to present a new concept of a radix-r Fast Fourier Transform (FFT), in which the radix-r butterfly computation concept was formulated as composite engines to implement each of the butterfly computations. This concept enables the radix r butterfly-processing element (BPE) to be designed by maintaining only one complex value multiplier in the butterfly critical path for any given r [2]. Algorithmic description and performance of low complexity FFT methods are considered in this paper where the speed and accuracy evaluation of the proposed method in fixed point is also elaborated.

Performances of Texas Instruments DSP and Xilinx FPGAs for Cooley-Tukey and Grigoryan FFT Algorithms

Abstract: Frequency analysis plays a vital role in the applications like cryptanalysis, steganalysis, system identification, controller tuning, speech recognition, noise filters, etc. Discrete Fourier transform (DFT) is a principal mathematical method for the frequency analysis. The way of splitting the DFT gives out various fast algorithms. In this paper, we present the implementation of two fast algorithms for the DFT for evaluating their performance. One of them is the popular radix-2 Cooley-Tukey fast Fourier transform (FFT) algorithm and the other one is the Grigoryan FFT based on the splitting by the paired transform. We evaluate the performance of these algorithms by implementing them on the TMS320C5416 DSP and also on the Virtex-II FPGAs. Finally, we show that the paired-transform-based algorithm of the FFT is faster than the radix-2 FFT; consequently, it is useful for higher sampling rates. We also discuss the performances of TMS DSP and Xilinx FPGAs and tradeoffs.

Power system harmonic analysis based on windowed FFT and wavelet transform

Abstract: Harmonics in power system are harmful to power network. In order to analyze power system harmonic more accurately, a new harmonic analysis algorithm based on interpolating windowed FFT and wavelet transform is proposed. This approach overcomes the shortcoming of FFT having frequency domain localization ability, but without time-domain localization ability. In this paper, the original signal is decomposed into the high-frequency component and the low-frequency component by the discrete wavelet transform. The low-frequency part is analyzed by interpolating windowed FFT algorithm to get the amplitude and phase of every steady harmonic. Simulation experiments are conducted with Matlab. The experimental results show that this method can not only analyze the steady-state harmonic accurately, but also inspect non-steady harmonics effectively.

Discontinuous Fast Fourier Transform with Triangle Mesh for Two-dimensional Discontinuous Functions

Abstract: In computational electromagnetics and other areas of computational science, Fourier transforms of discontinuous functions are frequently encountered This paper extends the discontinuous fast Fourier transform (DFFT) algorithm which was presented previously by Fan and Liu to deal with the two dimensional (2-D) function with a discontinuous boundary of arbitrary shape First, the proposed algorithm discretizes the support domain of the function by triangle mesh, which reduces the stair-casing error of an orthogonal grid required by FFT Second, the algorithm adopts the basic idea of double interpolation used by the original 1-D DFFT algorithm in the literature, but with a significant modification that the nonuniform fast Fourier transform (NUFFT) with the least square error (LSE) interpolation other than a Lagrange interpolation is used to process nonuniformly spaced samples of the exponentials The proposed 2-D DFFT algorithms obtain much higher accuracy than the conventional 2-D FFT for the discontinuous

Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization

Abstract: This paper reports the optimization of area and power for a 32-point radix-2 hybrid FFT (Fast Fourier Transform). The strategy consists of using the Constant Matrix Multiplication (CMM) method along the stages of the 8-point FFT architecture, which is implemented with Carry Save Adders (CSA). The use of CMM at gate level enables the replacement of the multiplication operations by addition/subtractions and shifts for each stage of the real and imaginary parts of the butterflies. The 32-point FFT is obtained through the composition of the optimized 8-point FFT modules. The partial decomposition of coefficients allows the computation of all coefficients necessary for the 32-point through a control unit. We have compared our proposed architecture to an implemented behavioral, unrestricted architecture synthesized using the CADENCE Encounter RTL Compiler for the UMC130nm technology. The results show reductions up to 31% in area and 15% in power when using our proposed solution.

Pruning split-radix FFT with time shift

Abstract: Eliminating computations on zeros when the number of nonzero inputs is considerably less than the length of Fast Fourier Transform (FFT) is considered as one of the methods to increase the computational efficiency of an FFT algorithm. This paper proposes a new split-radix FFT pruning algorithm with time shift for consecutive partial inputs. The shifting simplifies the flow graph in the first few stages of the pruning algorithm and makes the algorithm architecturally efficient. Comparisons of the computational complexity for the proposed split-radix FFT pruning algorithm with other algorithms show that the proposed method is more computationally efficient. Optimized hardware design based on this algorithm is also devised.

Design of data adaptive IFFT/FFT block for OFDM system

Abstract: Inverse Fast Fourier Transform/ Fast Fourier Transform (IFFT/FFT) processors are crucial blocks for an Orthogonal Frequency Division Multiplexing (OFDM) transceiver system. However, in the current OFDM systems, the system complexity and processing rate do not vary adaptively with the input data. In this paper, we propose a novel IFFT/FFT architecture for the OFDM Transceiver system that exploits the correlation between bytes of incoming information to adaptively choose between the Radix-2 and Radix • 4 algorithm. Using this architecture, we have achieved additional free data slots per frame. The transceiver system has been tested end-to-end and implemented on FPGA Board.

Mixed Precision Method for GPU-based FFT

Abstract: In order to solve the low accuracy problem of GPU-based FFT, a mixed precision method is employed in this paper. A "precision cache" method is proposed as the supplement of the mixed precision method to calculate of twiddle factor. A work group split method is used to reduce the latency of access global memory frequently. The mixed precision FFT achieves 3 times accuracy improvement compared to CUFFT3.2 and 4 times peak performance to MKL FFT. The experiment shows that mixed precision method on CPU-GPU heterogeneous platform achieves high accuracy and efficient Fast Fourier Transform.

A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system *

Abstract: The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system and the key technology in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. Since 3780 is not a power of 2, the classical radix-2 or radix-4 FFT algorithm cannot be applied directly. Hence, the Winograd Fourier transform algorithm (WFTA) and the Good-Thomas prime factor algorithm (PFA) are used to implement the 3780-point FFT processor. However, the structure based on WFTA and PFA has a large computational complexity and requires many DSPs in hardware implementation. In this paper, a novel 3780-point FFT processor scheme is proposed, in which a 60×63 iterative WFTA architecture with different mapping methods is imported to replace the PFA architecture, and an optimized CoOrdinate Rotation DIgital Computer (CORDIC) module is used for the twiddle factor multiplications. Compared to the traditional scheme, our proposed 3780-point FFT processor scheme reduces the number of multiplications by 45% at the cost of 1% increase in the number of additions. All DSPs are replaced by the optimized CORDIC module and ROM. Simulation results show that the proposed 3780-point FFT processing scheme satisfies the requirement of the DMB-T standard, and is an efficient architecture for the TDS-OFDM system.

ASIC implementation of a 512-point FFT/IFFT processor for 2D CT image reconstruction algorithm

Abstract: The CT scan medical imaging requires huge amount of computations for reconstructing the images. Modified Fast Radon Transform (MFRT) uses FFT based parallel algorithm for reconstruction of 2D/3D CT images from its sonogram data using convolution operation by concurrent 1D FFT/IFFT and matrix multiplications. To achieve optimum hardware utilization with low power consumption an FFT module, based on iterative radix-2 decimation in frequency (DIF) algorithm, has been designed and implemented. The module has been designed in such way so that it can also be used for IFFT computation only by changing a single parameter. To compute the FFT, the twiddle factor has been calculated using Coordinate Rotation Digital Computer (CORDIC), by steering the data properly in the butterfly structure. The synthesized frequency of FFT/IFFT module is 220 MHz and gate count is 1,040,136 using 130 nm faraday digital libraries. The power has been analyzed using prime power and the value of the power consumption is 15mW. The designed FFT/IFFT ASIC chip is very much suitable for low-area and low power biomedical applications like CT image reconstruction, Doppler wave spectrogram etc.

A shape contour description method based on chain code and Fast Fourier Transform

Abstract: A new shape contour description method based on eight-direction chain code and Fast Fourier Transform (FFT) is proposed. Firstly, chain code tracks shape boundary sequentially, according to the relationship between contour and chain-code projection-transform value. A constructed chain-code function of contour is transformed using FFT. After optimization, then a new Fourier Constant Factor Descriptor is proposed which is called FCFD. The descriptor is independent of initial point and has rotation, shift and scale (RSS) invariant properties. The results of experiments show that our shape contour description method based on FFT reduces computation and improves the efficiency of data processing effectively.

Generation of 1D and 2D FFT Function in MATLAB

Abstract: This paper proposes the generation of the code for the algorithm of 1D and 2D FFT and the methods for the recognition of faces using various methods of Joint Transform Correlation techniques. Various codes were written in MATLAB for the correlation and recognition of various images. Comparison between DFT and FFT Computation Speeds is made in this paper From results it is evident that for a couple of samples of various lengths the time taken by normal DFT is higher than the time taken by FFT. Thus the speed of FFT is beneficial when large calculations are required.