Showing papers on "Split-radix FFT algorithm published in 2014"

The Hopping Discrete Fourier Transform [sp Tips&Tricks]

Abstract: The discrete Fourier transform (DFT) produces a Fourier representation for finite-duration data sequences. In addition to its theoretical importance, the DFT plays a key role in the implementation of a variety of digital signal-?processing algorithms. Several algorithms including the fast Fourier transform (FFT) and the Goertzel algorithm have been introduced for the fast implementation of the DFT [1], [2].

High-precision Fourier forward modeling of potential fields

Abstract: We analyzed the numerical forward methods in the Fourier domain for potential fields. Existing Fourier-domain forward methods applied the standard fast Fourier transform (FFT) algorithm to inverse transform a conjugate symmetrical spectrum into a real field. It had significant speed advantages over space-domain forward methods but suffered from problems including aliasing, imposed periodicity, and edge effect. Usually, grid expansion was needed to reduce these errors, which was equivalent to the numerical evaluation of the oscillatory Fourier integral using the trapezoidal rule with smaller steps. We tested a high-precision Fourier-domain forward method based on a combined use of shift-sampling technique and Gaussian quadrature theory. The trapezoidal rule applied by the standard FFT algorithm to evaluate the continuous Fourier transform was modified by introducing a shift parameter ξ. By choosing optimum values of ξ as Gaussian quadrature nodes, we developed a Gauss-FFT method for Fourier forward modeling of potential fields. No grid expansion was needed, the sources can be set near the boundary of the fields or even go beyond the boundary. The Gauss-FFT method converged to the space-domain solution much faster than the standard FFT method with grid expansion. Forward modeling results almost identical to space-domain ones can be obtained in less time. Numerical examples, of both simple and complex 2D and 3D source forward modeling, revealed the reliability and adaptability of the method.

27.4 A 0.75-million-point fourier-transform chip for frequency-sparse signals

Abstract: Applications like spectrum sensing, radar signal processing, and pattern matching by convolving a signal with a long code, as in GPS, require large FFT sizes. ASIC implementations of such FFTs are challenging due to their large silicon area and high power consumption. However, the signals in these applications are sparse, i.e., the energy at the output of the FFT/IFFT is concentrated at a limited number of frequencies and with zero/negligible energy at most frequencies. Recent advances in signal processing have shown that, for such sparse signals, a new algorithm called the sparse FFT (sFFT) can compute the Fourier transform more efficiently than traditional FFTs [1].

Phase-unwrapping algorithm by a rounding-least-squares approach

Abstract: A simple and efficient phase-unwrapping algorithm based on a rounding procedure and a global least-squares minimization is proposed. Instead of processing the gradient of the wrapped phase, this algorithm operates over the gradient of the phase jumps by a robust and noniterative scheme. Thus, the residue-spreading and over-smoothing effects are reduced. The algorithm’s performance is compared with four well-known phase-unwrapping methods: minimum cost network flow (MCNF), fast Fourier transform (FFT), quality-guided, and branch-cut. A computer simulation and experimental results show that the proposed algorithm reaches a high-accuracy level than the MCNF method by a low-computing time similar to the FFT phase-unwrapping method. Moreover, since the proposed algorithm is simple, fast, and user-free, it could be used in metrological interferometric and fringe-projection automatic real-time applications.

Scaled Radix-2/8 Algorithm for Efficient Computation of Length- $N=2^{m}$ DFTs

Abstract: This paper presents a scaled radix-2/8 fast Fourier transform (FFT) (SR28FFT) algorithm for computing length- N = 2m discrete Fourier transforms (DFTs) scaled by complex number rotating factors. The idea of the SR28FFT algorithm is from the modified split radix FFT (MSRFFT) algorithm, and its purpose is to furnish other algorithms with high efficiency but without shortcomings of the MSRFFT algorithm. A novel radix-2/4 FFT (NR24FFT) algorithm and a novel radix-2/8 FFT (NR28FFT) algorithm are proposed. These two algorithms use SR28FFT to calculate their sub-DFTs of odd-indexed terms. Several aspects of the two algorithms such as computational complexity, computation accuracy, and coefficient evaluations or accesses to the lookup table all are improved. The bit-reverse method can be used for their order permutation and no extra memory is required to store their extra coefficients by the two novel algorithms, which contribute significantly to the performance of the FFT algorithms. The SR28FFT algorithm can also be applied to other algorithms whose decomposition contains sub-DFTs of powers-of-two. The Appendix presents an algorithm named SR28FFT-2 for further reducing the number of arithmetic operations, and NR24FFT and NR28FFT algorithms based on SR28FFT-2 requires fewer real operations than that required by the MSRFFT algorithm.

Exact image representation via a number-theoretic radon transform

Abstract: This study presents an integer-only algorithm to exactly recover an image from its discrete projected views that can be computed with the same computational complexity as the fast Fourier transform (FFT). Most discrete transforms for image reconstruction rely on the FFT, via the Fourier slice theorem (FST), in order to compute reconstructions with lowcomputational complexity. Consequently, complex arithmetic and floating point representations are needed, the latter of which is susceptible to round-off errors. This study shows that the slice theorem is valid within integer fields, via modulo arithmetic, using a circulant theory of the Radon transform (RT). The resulting number-theoretic RT (NRT) provides a representation of images as discrete projections that is always exact and real-valued. The NRT is ideally suited as part of a discrete tomographic algorithm, an encryption scheme or for when numerical overflow is likely, such as when computing a large number of convolutions on the projections. The low-computational complexity of the NRT algorithm also provides an efficient method to generate discrete projected views of image data.

Fast Fourier Transform (FFT)

Abstract: Data can be described either in the “time domain” or in the “frequency domain”. The frequency domain representations present details about the same signal in a different, potentially more illuminating way. The fast Fourier transform (FFT) provides a fast computational algorithm to obtain the coefficients of the discrete-frequency representation. Keywords: DFT ; FFT ; spectral analysis; computational efficiency

FFT Key Recovery for Integral Attack

Abstract: An integral attack is one of the most powerful attacks against block ciphers. We propose a new technique for the integral attack called the Fast Fourier Transform FFT key recovery. When the integral distinguisher uses N chosen plaintexts and the guessed key is k bits, a straightforward key recovery requires the time complexity of ON 2 k . However, the FFT key recovery method requires only the time complexity of ON+k 2 k . As a previous result using FFT, at ICISC 2007, Collard et al.proposed that FFT can reduce the time complexity of a linear attack. We show that FFT can also reduce the complexity of the integral attack. Moreover, the estimation of the complexity is very simple. We first show the complexity of the FFT key recovery against three structures, the Even-Mansour scheme, a key-alternating cipher, and the Feistel cipher. As examples of these structures, we show integral attacks against PrOst, CLEFIA, and AES. As a result, 8-round PrOst $\tilde{P}_{128,K}$ can be attacked with about an approximate time complexity of 280. Moreover, a 6-round AES and 12-round CLEFIA can be attacked with approximate time complexities of 252.6 and 287.5, respectively.

FFT algorithm of complex exponent moments and its application in image recognition

Abstract: Orthogonal multi-distorted invariant Complex Exponent Moments (CEMs) are proposed. A fast and accurate 2-D Fast Fourier Transform (FFT) algorithm is used to calculate CEMs. Theoretical analysis is presented to demonstrate the multi-distorted invariant property of CEMs. The proposed method is applied in the pattern recognition of human faces, English letters and Chinese characters. Experimental results show that CEMs have higher quality and lower computational complexity than RHFMs in image reconstruction and pattern recognition.

A 128∶2048/1536 point FFT hardware implementation with output pruning

Abstract: In this work, an FFT architecture supporting variable FFT sizes, 128∼2048/1536, is proposed. This implementation is a combination of a 2 point Common Factor FFT and a 3 point DFT. Various FFT output pruning techniques for this architecture are discussed in terms of memory and control logic overhead. It is shown that the used Prime Factor FFT as an FFT in the 1536 point FFT is able to increase throughput by exploiting single tone pruning with low control logic overhead. The proposed FFT processor is implemented on a Xilinx Virtex 5 FPGA. It occupies only 3148 LUTs and 612 kb memory in FGPA and calculates 1536 point FFT less than 3092 clock cycles with output pruned settings.

A CORDIC-friendly FFT architecture

Abstract: Fast Fourier Transform (FFT) is one of the basic building blocks in signal processing and communications systems. The butterflies-based structure of the FFT is the main reason for the reduced number of arithmetic operations required to implement the transform. From implementation point of view, the complex rotations used in butterflies can be implemented by using COordinate Rotation DIgital Computer (CORDIC). This implementation strategy reduces the hardware complexity compared to the direct implementation of the butterflies using complex multipliers. In this paper, we introduce a restructure of the butterflies of the radix-2 FFT to be more CORDIC friendly. This algorithm-level modification of the FFT is friendly towards all CORDIC types, including those introducing non-fixed gain. Compared with the conventional radix-2 FFT algorithm, the proposed algorithm introduces a substantial increase in performance. For example, it achieves superior signal to quantization noise ratio (SQNR), with around 14 dB gain for 8 to 1024 points FFT. In addition, in pipeline architectures the modification leads to an improvement in latency or a reduction in the total area, with an improvement in either of 38% for 1024 points FFT.

Fast and accurate simulation of the turbulent phase screen using fast Fourier transform

Abstract: This work describes an accurate method for simulating turbulent phase screens. The phase screen is divided into a fast Fourier transform (FFT)-based screen and a tilt screen. The simulation of the FFT-based screen is different from that of the standard method. In the simulation, the discrete power spectrum of the turbulence is obtained from the discrete Fourier transform of the phase autocorrelation matrix, not from the theoretical power spectrum. This method avoids the drawbacks of the undersampling of the low frequency and high frequency components which occurs in the standard FFT-based method. The maximum error in the phase structure function can be reduced to <0.13% , and the additional execution time increases by only several percents. This method is only suitable for square screens.

FPGA implementation of low-power split-radix FFT processors

Abstract: Fast Fourier Transform (FFT) is one of the fundamental operations in digital signal processing area. Splitradix Fast Fourier Transform (SRFFT) approximates the minimum number of multiplications by theory among all the FFT algorithms, therefore SRFFT is a good candidate for the implementation of a low power FFT processor. In this PhD work, we aim to implement a novel low power Split-Radix FFT processor using shared-memory architecture and extend this work to a parallel structure based on FPGA. We started by designing a new radix-2 butterfly unit using clock gating approach to block unnecessary switching activity in the multiplier. Compared to existing SRFFT processors which are based on the “L” shaped butterfly, our implementation simplifies the address generation process for FFT data. Furthermore, because the number of multiplications required by SRFFT algorithm significantly decreases as the FFT size increases, it is reasonable to assume the proposed architecture will save more power when it comes to larger points of FFT.

A Radix-2 DIT FFT with Reduced Arithmetic Complexity

Abstract: The efficient computation of Discrete Fourier Transform (DFT) is an important issue as it is used in almost all fields of engineering for signal processing. This paper presents a different form of Radix-2 Fast Fourier Transform (FFT) based on Decimation in time (DIT) to compute DFT, discuss their implementation issues and derive it's signal to quantization noise ratio(SQNR) that further decreases the number of multiplication counts without affecting the number of additions of Radix-2 discrete Fourier Transform. It is achieved by simple scaling of Twiddle factor (TF) using a special scaling factor. This modification not only decreases the total flop counts from 5Nlog(2)N to approximate to 4 2/3Nlog(2)N (6.66% fewer than the standard Radix-2 FFT algorithm) but also improves SQNR from to 1/2N2(-2b) to 9/15N2(-2b) (1. 6dB more than the standard Radix-2 FFT algorithm).

New quantization error assessment methodology for fixed-point pipeline FFT processor design

Abstract: Since the blooming of mobile computing era, all semiconductor providers are seeking to provide low-power, high-performance, high-compact solutions to consumers. System on Chip (SoC) is a prominent solution for integrating multiple functions into one compact size chip. However, for many new applications with high intensive computing demands, such as GPS location, High Definition (HD) video recording and processing, Orthogonal Frequency-Division Multiplexing (OFDM), etc. System designers usually utilize fixed point algorithms other than floating-point algorithms as a trade-off between precession and memory occupation. One of the challenging works in designing a fixed-point FFT processor is to assess the quantization error introduced by wordlength configuration. An optimized wordlength configuration will eliminate the output quantization error in some extent, and save a large amount of memory space, which has become a crucial part of SoC/ASIC design. In this paper, we proposed a quantization error model based method to assess the output SQNR (Signal-to-Quantization-Noise Ratio), and we thoroughly discussed a matrix representation of a radix-22 Decimation-In-Frequency (DIF) FFT quantization error propagation model. In addition, we comprehensively analyze and disclose the quantitative relationships among wordlength configuration, fixed-point FFT architecture and output SQNR. A new wordlength configuration method named PMBM (Performance-Memory Balanced Method) for fixed-point pipeline FFT processor is also proposed. Eventually, we testified our method in both a 256-point FFT and a 1024-point FFT using SystemC platform. The experiment results show that our method significantly decrease the memory usage of a pipeline FFT by 26% (256-point) and 30% (1024-point) respectively. We implemented a 16K-point FFT ASIC to verify our method.

An efficient folded pipelined architecture for Fast Fourier Transform using Cordic algorithm

Abstract: Fast Fourier Transforms have become an integral part of any digital communication system and a wide variety of approaches have been tried in order to optimize the algorithm for a variety of parameters, primarily being memory and speed. Major problem in FFT calculation is the increased number of complex multiplication units. Folding transformations are used to design FFT architectures with reduced number of functional units. In the folding transformation, many butterflies in the same column can be mapped to one butterfly unit. A highly efficient pipelined folded FFT architecture for 8 point R2 FFT is presented here. When compared with the normal R2 FFT architecture, the pipelined architecture shows efficiency both in speed and area consumption. Futher reduction in the area can be obtained by using COordinate Rotation for DIgital Computer (CORDIC) algorithm, which is an add and shift algorithm that replaces complex twiddle factor multiplication. The FFT block is designed to be capable of computing 8 point FFT and employs R2 (Radix2) architecture which is simple, elegant and best suited for communication applications. VHDL coding is simulated and synthesized in Xilinx ISE Design Suite 12.1.

Fft based solution for multivariable l2 equations using kkt system via fft and efficient pixel-wise inverse calculation

Abstract: When solving l 2 optimization problems based on linear filtering with some regularization in signal/image processing such as Wiener filtering, the fast Fourier transform (FFT) is often available to reduce its computational complexity. Most of the problems, in which the FFT is used to obtain their solutions, are based on single variable equations. On the other hand, the Karush-Kuhn-Tucker (KKT) system, which is often used for solving constrained optimization problems, generally results in multivariable equations. In this paper, we propose a FFT based computational method for multivariable l 2 equations. Our method applies a FFT to each block of the KKT system, and represents the equation as an image-wise simultaneous equation consisting of Fourier transformed filters and images. In our method, an inverse matrix calculation that consists of complex pixel values gathered from each transformed image is required for each pixel. We exploit the homogeneity of neighboring values and solve them efficiently.

Low power reconfigurable FP-FFT core with an array of folded DA butterflies

Abstract: A variable length (32 ~ 2,048), low power, floating point fast Fourier transform (FP-FFT) processor is designed and implemented using energy-efficient butterfly elements. The butterfly elements are implemented using distributed arithmetic (DA) algorithm that eliminates the power-consuming complex multipliers. The FFT computations are scheduled in a quasi-parallel mode with an array of 16 butterflies. The nodes of the data flow graph (DFG) of the FFT are folded to these 16 butterflies for any value of N by the control unit. Register minimization is also applied after folding to decrease the number of scratch pad registers to (log 2 N − 1) × 16. The real and imaginary parts of the samples are represented by 32-bit single-precision floating point notation to achieve high precision in the results. Thus, each sample is represented using 64 bits. Twiddle factor ROM size is reduced by 25% using the symmetry of the twiddle factors. Reconfigurability based on the sample size is achieved by the control unit. This distributed floating point arithmetic (DFPA)-based design of FFT processor implemented in 45-nm process occupies an area of 0.973 mm2 and dissipates a power of 68 mW at an operating frequency of 100 MHz. When compared with FFT processor designed in the same technology with multiplier-based butterflies, this design shows 33% less area and 38% less power. The throughput for 2,048-point FFT is 222 KS/s and the energy spent per FFT is 7.4 to 14 nJ for 64 to 2,048 points being one among the most energy-efficient FFT processors.

A Fast Algorithm Based on SRFFT for Length $N = q\times 2^{m}$ DFTs

Abstract: In this brief, we present a fast algorithm for computing length- q×2m discrete Fourier transforms (DFT). The algorithm divides a DFT of size- N = q×2m decimation in frequency into one length- N/2 DFT and two length- N/4 DFTs. The length- N/2 sub-DFT is recursively decomposed decimation in frequency, and the two size- N/4 sub-DFTs are transformed into two dimension and the terms with the same rotating factor are arranged in a column. Thus, the scaled DFTs (SDFTs) are obtained, simplifying the real multiplications of the proposed algorithm. A further improvement can be achieved by the application of radix-2/8, modified split-radix FFT (MSRFFT), and Wang's algorithm for computing its length- 2m and length- q sub-DFTs. Compared with the related algorithms, a substantial reduction of arithmetic complexity and more accurate precision are obtained.

Distributed Arithmetic based Split-Radix FFT

Abstract: In this paper we have designed a Split-radix type FFT unit without using multipliers. All the complex multiplications required for this type of FFT are implemented using Distributed Arithmetic (DA) technique. A method is incorporated to overcome the result overflow problem introduced by DA method. Proposed FFT architecture is implemented in 180 nm CMOS technology at a supply voltage of 1.8 V.

VLSI implementation of efficient split radix FFT based on distributed arithmetic

Abstract: Fast Fourier Transform (FFT) is a very common operation used for various signal processing units. Many efficient algorithms are being designed to improve the architecture of FFT. Among the different algorithms, split-radix FFT has shown considerable improvement in terms of reducing hardware complexity of the architecture compared to radix-2 and radix-4 FFT algorithm. The performance in terms of throughput of the processor is limited by the multiplication. Therefore multiplier is optimized to make the input to output delay as short as possible. Distributed arithmetic (DA) is one of the most used techniques in implementing multiplier-less architectures of many digital systems. In this paper a Split Radix FFT without the use of multiplier is designed. All the complex multiplications are done by using Distributed Arithmetic (DA) technique. For faster calculation parallel prefix adder is used. These algorithms reduces overall arithmetic operations in FFT, but increases the number of operations and complexity of each butterfly. In Split Radix FFT, mixed-radix approach helps to achieve low number of multiplications and additions. The advantage of DA is its efficiency of mechanization. A method is incorporated to overcome the overflow problem introduced by DA method.

Simplified addressing scheme for mixed radix FFT algorithms

Abstract: A mixed radix algorithm for the in-place fast Fourier transform (FFT), which is broadly used in most embedded signal processing fields, can be explicitly expressed by an iterative equation based on the Cooley-Tukey algorithm. The expression can be applied to either decimation-in-time (DIT) or decimation-in-frequency (DIF) FFTs with ordered inputs. For many newly emerging low power portable computing applications, such as mobile high definition video compressing, mobile fast and accurate satellite location, etc., the existing methods perform either resource consuming or non-flexible. In this paper, we propose a new addressing scheme for efficiently implementing mixed radix FFTs. In this scheme, we elaborately design an accumulator that can generate accessing addresses for the operands, as well as the twiddle factors. The analytical results show that the proposed scheme reduces the algorithm complexity meanwhile helps the designer to efficiently choose an arbitrary FFT to design the in-place architecture.

Pipelined FFT architectures for real-time signal processing and wireless communication applications

Abstract: This paper proposes two-parallel pipelined fast Fourier transform (FFT) architectures for the discrete Fourier transform (DFT) computation of real-valued signals. The architectures are optimized with less number of registers for signal processing and wireless communication applications. The clock to registers is disabled to avoid storing of the redundant values and hence the registers actually storing those redundant values are eliminated. The proposed architectures requires 22% less registers than the prior architectures. The real-valued FFT (RFFT) processor is further optimized to process BPSK outputs in which case 43% of register is reduced.

Comparative Study of Influence of Noise on Power Frequency Estimation of Sine wave Using Interpolation FFT

Abstract: This paper compares performances of frequency estimations provided by different interpolation fast Fourier transform (FFT) algorithms under white Gaussian noises. Firstly, accuracies of frequency estimation algorithms are evaluated by deriving analytical expressions of variances of frequency estimation. Then, theoretical results are validated by means of computer simulations. It is shown that the trade-off between biases and variances of frequency estimation is unavoidable. From both theoretical and simulation results, it can be concluded that variances of frequency estimation are proportional to the noise variance and inverse proportional to the length of FFT.

A novel low-power and in-place split-radix FFT processor

Abstract: Split-radix Fast Fourier Transform (SRFFT) approximates the minimum number of multiplications by theory among all the FFT algorithms. Since multiplications significantly contribute to the overall system power consumption, SRFFT is a good candidate for implementation of a low power FFT processor. In this paper we present a novel low power SRFFT processor using a modified radix-2 butterfly structure. With the proposed butterfly unit, the address generation scheme for conventional radix-2 FFT could be applied to SRFFT and therefore it can avoid the complexity of address generation and interim data registers. Simulation results show that compared with a conventional radix-2 implementation, power consumption of the new processor is reduced by an amount of 11.7% and 18.3% for 16-point and 32-point FFT respectively.

High Performance Computing for a Financial Application Using Fast Fourier Transform

Abstract: Fast Fourier Transform (FFT) has been used in many scientific and engineering applications. In the current study, we have applied the FFT for a novel application in finance. We have improved a mathematical model of Fourier transform technique for pricing financial derivatives to help design an effective parallel algorithm. We have then developed a new parallel algorithm for FFT using a swapping technique that exploits data locality. We have analyzed our algorithm theoretically and have reported the significance of the new algorithm. We have implemented our algorithm on 20 node SunFire 6800 high performance computing system and compared the new algorithm with the traditional Cooley-Tukey algorithm both as stand alone comparison of the performance and in relation to our theoretical analysis and showed higher efficiency of our algorithm. We have presented the computed option values for various strike prices with a proper selection of strike-price spacing to ensure fine-grid integration for FFT comput...

Enhancing the quality of voice communications by acoustic noise cancellation (ANC) using a low cost adaptive algorithm based Fast Fourier Transform (FFT) and circular convolution

Abstract: In this paper a module consisting of a Fast Least Mean Square (FLMS) filter is modeled and verified to eliminate acoustic noise, which is a problem in voice communication. However the acoustic noise cancellation (ANC) is modeled using digital signal processing technique especially Simulink Blocksets. The needed algorithm code is generated in Matlab Simulink programming. At the simulation level, results of simulink implementation prove the module behavior for cancellation of noise in voice communication using the FLMS adaptive algorithm. The main scope of this paper is to implement the module, benefiting the advantage of DFT (Discrete Fourier transform) circular convolution properties and Fast Fourier Transform (FFT) high computation speed in frequency domain rather adaptive algorithms Normalized Least Mean Square (NLMS) and Recursive Least Square (RLS) in time domain with high complexity, also the simplicity of the implementation using simulink programming.

ASIC implementation of high speed fast fourier transform based on Split-radix algorithm

Abstract: Mathematical applications such as DFT and convolution are two main and common operations in signal processing applications. Many other Signal processing algorithms such as filter, spectrum estimation and OFDM can be transformed into DFT to implement in hardware. FFT is the collection of group of algorithms that performs the DFT at higher speed. FFT is indispensable in most signal processing applications, so the designing of an appropriate algorithm for the implementation of FFT can be most important in Most of the digital signal processing. The techniques such as pipelining and parallel calculations have potential impacts on VLSI implementation of FFT algorithm. By theoretical observations Split-radix algorithm is an appropriate algorithm for the implementation of FFT among all the effective algorithms of FFT, because it reduces number of arithmetic operations to great extent. At the requirement of high speed, an algorithm that is best for high speed implementation is to be found. This algorithm performs well in the implementation of FPGA and ASIC, satisfies the requirement of high speed.