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Split-radix FFT algorithm

About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.


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Proceedings ArticleDOI
06 Nov 2014
TL;DR: A quantization error model based method to assess the output SQNR (Signal-to-Quantization-Noise Ratio) and a new wordlength configuration method named PMBM (Performance-Memory Balanced Method) for fixed-point pipeline FFT processor is proposed.
Abstract: Since the blooming of mobile computing era, all semiconductor providers are seeking to provide low-power, high-performance, high-compact solutions to consumers. System on Chip (SoC) is a prominent solution for integrating multiple functions into one compact size chip. However, for many new applications with high intensive computing demands, such as GPS location, High Definition (HD) video recording and processing, Orthogonal Frequency-Division Multiplexing (OFDM), etc. System designers usually utilize fixed point algorithms other than floating-point algorithms as a trade-off between precession and memory occupation. One of the challenging works in designing a fixed-point FFT processor is to assess the quantization error introduced by wordlength configuration. An optimized wordlength configuration will eliminate the output quantization error in some extent, and save a large amount of memory space, which has become a crucial part of SoC/ASIC design. In this paper, we proposed a quantization error model based method to assess the output SQNR (Signal-to-Quantization-Noise Ratio), and we thoroughly discussed a matrix representation of a radix-22 Decimation-In-Frequency (DIF) FFT quantization error propagation model. In addition, we comprehensively analyze and disclose the quantitative relationships among wordlength configuration, fixed-point FFT architecture and output SQNR. A new wordlength configuration method named PMBM (Performance-Memory Balanced Method) for fixed-point pipeline FFT processor is also proposed. Eventually, we testified our method in both a 256-point FFT and a 1024-point FFT using SystemC platform. The experiment results show that our method significantly decrease the memory usage of a pipeline FFT by 26% (256-point) and 30% (1024-point) respectively. We implemented a 16K-point FFT ASIC to verify our method.

10 citations

Patent
03 Mar 1975
TL;DR: In this paper, two kinds of apparatus for combining N 2 chirp-Z transform (CZT) modu of length n 1 to perform a discrete Fourier transform (DFT) of length N 1 N 2.
Abstract: Two kinds of apparatus for combining N 2 chirp-Z transform (CZT) modu of length N 1 to perform a discrete Fourier transform (DFT) of length N 1 N 2 . The first method uses an auxiliary parallel-input, parallel-output, DFT device of size N 2 and allows the transform of size N 1 N 2 to be performed in the same time as is required for a single CZT module to perform a size N 1 transform. The second method uses an auxiliary parallel-input, serial-output, DFT device of size N 2 . If the second method is implemented entirely in a single technology, such as with charge-coupled devices (CCDs), it performs the size N 1 N 2 transform in N 2 times the amount of time required for a single CZT module to perform a size N 1 transform. If N 2 is a composite number, say N 2 = M 1 M 2 , the second method also permits the same hardware to perform M 1 simultaneous transforms of length N 1 M 2 .

10 citations

Proceedings ArticleDOI
08 May 2014
TL;DR: A highly efficient pipelined folded FFT architecture for 8 point R2 FFT is presented here and shows efficiency both in speed and area consumption.
Abstract: Fast Fourier Transforms have become an integral part of any digital communication system and a wide variety of approaches have been tried in order to optimize the algorithm for a variety of parameters, primarily being memory and speed. Major problem in FFT calculation is the increased number of complex multiplication units. Folding transformations are used to design FFT architectures with reduced number of functional units. In the folding transformation, many butterflies in the same column can be mapped to one butterfly unit. A highly efficient pipelined folded FFT architecture for 8 point R2 FFT is presented here. When compared with the normal R2 FFT architecture, the pipelined architecture shows efficiency both in speed and area consumption. Futher reduction in the area can be obtained by using COordinate Rotation for DIgital Computer (CORDIC) algorithm, which is an add and shift algorithm that replaces complex twiddle factor multiplication. The FFT block is designed to be capable of computing 8 point FFT and employs R2 (Radix2) architecture which is simple, elegant and best suited for communication applications. VHDL coding is simulated and synthesized in Xilinx ISE Design Suite 12.1.

10 citations

Proceedings ArticleDOI
12 Mar 2012
TL;DR: A new parallel FFT architecture which combines the split-radix algorithm with a constant geometry interconnect structure which achieves 46% lower power than a parallel radix-4 design at 4.5GS/s when computing a 128-point real-valued transform.
Abstract: High performance hardware FFTs have numerous applications in instrumentation and communication systems. This paper describes a new parallel FFT architecture which combines the split-radix algorithm with a constant geometry interconnect structure. The split-radix algorithm is known to have lower multiplicative complexity than both radix-2 and radix-4 algorithms. However, it conventionally involves an "L-shaped" butterfly datapath whose irregular shape has uneven latencies and makes scheduling difficult. This work proposes a split-radix datapath that avoids the L-shape. With this, the split-radix algorithm can be mapped onto a constant geometry interconnect structure in which the wiring in each FFT stage is identical, resulting in low multiplexing overhead. Further, we exploit the lower arithmetic complexity of split-radix to lower dynamic power, by gating the multipliers during trivial multiplications. The proposed FFT achieves 46% lower power than a parallel radix-4 design at 4.5GS/s when computing a 128-point real-valued transform.

10 citations

Proceedings ArticleDOI
05 Mar 2015
TL;DR: An architecture for real time hardware implementation of Hilbert Transform (HT) using Fast Fourier Transform (FFT) using Xilinx Kintex- 7 based FPGA is presented and the results acquired are presented in comparison to results obtained through MATLAB simulations.
Abstract: This paper presents an architecture for real time hardware implementation of Hilbert Transform (HT) using Fast Fourier Transform (FFT). HT is studied and its various application areas are discussed in the paper. Two different architectures are proposed using Fast Fourier Transform (FFT) for the implementation. Implementation of HT using the proposed FFT based architectures are compared with the implementations using Discrete Fourier Transform (DFT) and Discrete Hartley Transform (DHT). The proposed FFT based architectures are implemented on Xilinx Kintex- 7 based FPGA and the results acquired are presented in comparison to results obtained through MATLAB simulations. The architecture implemented supports transform length of 8192 points as a demonstrator to the idea using 24 bit fixed point arithmetic. Detailed comparison study in terms of resource utilization and timing analysis is also carried out and the results are reported.

10 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20239
202234
20192
20188
201748
201689