Split-radix FFT algorithm

About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.

FFT-Based Computation of Shift Invariant Analytic Wavelet Transform

Abstract: This letter introduces an analytic wavelet transform based on linear phase quadrature mirror filters (QMFs). The computation of the analytic signal and the reconstruction of the signal is carried by the fast Fourier transform (FFT)-based algorithm. The transform yields energy preserving and shift invariant decimated analytic wavelet coefficients, which are free of aliasing effects. The present method can be implemented in the microprocessor and VLSI environment using a commercial FFT chip

Faster than the FFT: The chirp-z RAG-n Discrete Fast Fourier Transform

Abstract: DFT and FFTs are important but resource intensive building blocks and have found many application in communication systems ranging from fast convolution to coding of OFDM signals. It has recently be shown that the n-Dimensional Reduced Adder Graph (RAG-n) technique is beneficially in many applications such as FIR or IIR filters, where multiplier can be grouped in multiplier blocks. This paper explores how the RAG-n technique can be applied to DFT algorithms. A RAG-n fast discrete Fourier transform will be shown to be of low latency and complexity and posses a VLSI attractive regular data flow when implemented with the Bluestein chirp-z algorithm. VHDL code synthesis results for Xilinx Virtex II FPGAs are provided and demonstrate the superior properties when compared with Xilinx FFT IP cores. Index Terms – Fast Fourier Transform, OFDM, FPGA, n-Dimensional Reduced Adder Graph

Design and implementation of a scalable fast Fourier transform core

Abstract: A novel approach for scalable length Fast Fourier Transform (FFT) in single Processing Element (single PE) architecture has been developed. The scalable length FFT design meets the different lengths requirement of FFT operation in an OFDM system. An efficient mechanism, named Interleaved Rotated Data Allocation (IRDA), to replace the multiple-port memory with a single-port memory has also been proposed. Using a single-port memory instead of multiple-port memory makes the design more area efficient.

A Novel VLSI Architecture for Image Compression

Abstract: In analog signal processing of multimedia applications, audio need not be compressed but video must be compressed in order to conserve the bandwidth. For this purpose fast cosine transform (FCT) is preferred, which is developed using fast Fourier transform (FFT). But it has several limitations of delays, area and power. In this paper the similarities among fast Fourier transform (FFT), fast cosine transform (FCT) and fast Hartley transform (FHT) have been studied. The converged very large scale integration (VLSI) architecture for these hybrid transforms for video compression are designed, simulated and synthesized. Implementing FCT, FFT, and FST from fast Hartley transform is developed and hybrid transforms architecture is proposed. Further more, delays and area overheads have been calculated. For all these transforms the layouts have been drawn using magma tools with 0.13 mum technology. Compression ratio for image with each transform and Hybrid transform is also implemented

Frequency Offset Estimation With Multi-Steps Interpolation for Coherent Optical Systems

Abstract: We investigate a frequency offset estimation (FOE) algorithm based on improved fast Fourier transform (FFT) for coherent optical systems. The algorithm implements FFT operation with a small number of samples and then adopts multi-steps interpolation with the increasing number of samples to improve the estimation accuracy gradually. In a 28-GBd coherent quaternary phase-shift keying system, simulation results show that the proposed algorithm reaches the same estimation accuracy with least-squares FOE algorithm that utilizes 64 time spans (LS-64) under the same total number of samples $L$ . But the number of complex multiplications required by the proposed algorithm is just 7.26% and 6.75% of that required by LS-64 at $L=1024$ and $L=2048$ , respectively.