Split-radix FFT algorithm

About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.

Sequential design of a 8192 complex point FFT in OFDM receiver

Abstract: In this paper we propose an implementation method for a single-chip 8192 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 8 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 8192-point FFT consists of the cascaded blocks with six stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result the proposed structure brings about the 55% chip size reduction compared with conventional approach.

VLSI implementation of efficient split radix FFT based on distributed arithmetic

Abstract: Fast Fourier Transform (FFT) is a very common operation used for various signal processing units. Many efficient algorithms are being designed to improve the architecture of FFT. Among the different algorithms, split-radix FFT has shown considerable improvement in terms of reducing hardware complexity of the architecture compared to radix-2 and radix-4 FFT algorithm. The performance in terms of throughput of the processor is limited by the multiplication. Therefore multiplier is optimized to make the input to output delay as short as possible. Distributed arithmetic (DA) is one of the most used techniques in implementing multiplier-less architectures of many digital systems. In this paper a Split Radix FFT without the use of multiplier is designed. All the complex multiplications are done by using Distributed Arithmetic (DA) technique. For faster calculation parallel prefix adder is used. These algorithms reduces overall arithmetic operations in FFT, but increases the number of operations and complexity of each butterfly. In Split Radix FFT, mixed-radix approach helps to achieve low number of multiplications and additions. The advantage of DA is its efficiency of mechanization. A method is incorporated to overcome the overflow problem introduced by DA method.

Application of zoom FFT technique to detecting EM signal of SLF/ELF

Abstract: Discrete fast Fourier transform (FFT) has been widely applied to signal spectral analysis and can figure out the entire bandwidth spectrum of a signal. However, the fine structure of high resolution spectrum in a narrow bandwidth is required in some applications. If regular FFT is still used to figure out the high resolution spectrum, it will result in addition of data and at last sharply increase of computation and storage. Therefore, FFT is inefficient and a new method must be put forward. In the paper, the principle of zoom FFT technique based on complex modulation, its application to development of SLF/ELF receiver and how to obtain high resolution spectrum using the new technique are introduced in detail and also the theoretical and test results are presented.

An efficient FFT algorithm for real-symmetric data

Abstract: A very efficient algorithm for computing the discrete Fourier transform (DFT) of real-symmetric input is presented. The algorithm is based on Bruun's algorithm where, except for the last stage, all twiddle factors are purely real. It is well-known that about half of the arithmetic operations and memory requirements can be removed when the input is real-valued. It may be assumed that another half of the computational and memory requirements can be eliminated when the input is real and symmetric. This is, however, impossible with a standard radix-2 fast Fourier transform (FFT), but can be achieved by the Bruun algorithm. The symmetries within the algorithm with for real-symmetric input are exploited to remove about three fourths of the butterflies and memory locations. The algorithm presented achieves the same low arithmetic as the split-radix FFT for real-symmetric data, but has a structure that is as simple as the radix-2. The implementation on the TMS320C30 shows that the new algorithm fits a DSP processor very well. The program requires 0.51-0.60 ms to compute a length 1024 FFT with real-symmetric data. >