Split-radix FFT algorithm

About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.

Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization

Abstract: This paper reports the optimization of area and power for a 32-point radix-2 hybrid FFT (Fast Fourier Transform). The strategy consists of using the Constant Matrix Multiplication (CMM) method along the stages of the 8-point FFT architecture, which is implemented with Carry Save Adders (CSA). The use of CMM at gate level enables the replacement of the multiplication operations by addition/subtractions and shifts for each stage of the real and imaginary parts of the butterflies. The 32-point FFT is obtained through the composition of the optimized 8-point FFT modules. The partial decomposition of coefficients allows the computation of all coefficients necessary for the 32-point through a control unit. We have compared our proposed architecture to an implemented behavioral, unrestricted architecture synthesized using the CADENCE Encounter RTL Compiler for the UMC130nm technology. The results show reductions up to 31% in area and 15% in power when using our proposed solution.

A parallel implementation method of FFT-based full-search block matching algorithms

Abstract: One category of fast full-search block matching algorithms (BMAs) is based on the fast Fourier transformation (FFT). This paper proposes a parallel implementation method of FFT-based full-search BMAs. The FFT-based full-search BMAs are much faster than the direct full-search BMA, and its accuracy is as same as the direct full-search BMA. However, these are not designed for parallel processing. The proposed method divides the search window into multiple sub search windows using the overlap-save method, and the FFT-based full-search BMA is applied to each sub search window. These sub search windows are processed in parallel. By dividing the search window, the method can not only process in parallel, but also select the efficient FFT size. Furthermore, the method can also calculate two cross-correlations at the same time. These properties also contribute to speeding up of the block matching. The experimental results shows that the method on 6 cores CPU is about 11 times faster than the conventional FFT-based full-search BMA.

Methods and systems using fft window tracking algorithm

Abstract: Techniques for the adjustment of a position of Fast Fourier Transform (FFT) window are provided. The adjustment may be based on the condition that the length of channel impulse response is larger than the length of cyclic prefix. The technique may determine a position of the FFT window that attempts to maximize carrier-to-noise (C/N) ratio value measured at the receiver.

Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors

Abstract: This paper proposes a shared multiplier scheduling scheme (SMSS) for area-efficient fast Fourier transform (FFT)/inverse FFT processors. SMSS can significantly reduce the total number of complex multipliers up to 28%. The proposed mixed-radix multipath delay commutator processors can support 128/256 and 256/512-point FFTs using SMSS. The proposed processors have been designed and implemented with 90-nm CMOS technology, which can reduce the total hardware complexity by 20%. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 27.5 GS/s at 430 MHz. In addition, the proposed processors can support any FFT size using additional stages.