Split-radix FFT algorithm

About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.

High-Throughput VLSI Architecture for FFT Computation

Abstract: In this brief, multi-path delay commutator structures are utilized to improve the throughput rate of radix-2 and radix-4 FFT computation by a factor of 2 to 4. Latency can also be reduced by a factor of 2 to 3. Compared with previous radix-2 and radix-4 FFT structures, the proposed high-throughput FFT with doubled throughput rate requires similar or even less hardware cost. Although split radix FFT design is more hardware efficient, the regular structure of proposed FFT structures are attractive for high throughput FFT design.

A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors

Abstract: In this brief, a generalized mixed-radix (GMR) algorithm is proposed for memory-based fast Fourier transform (FFT) processors to support prime-sized and traditional 2n -point FFTs simultaneously It transforms the index to a multidimensional vector for efficient computation By controlling the index vector to satisfy the ?vector reverse? behavior, the GMR algorithm can support not only in-place policy for both computation and I/O data for continuous data flow to minimize the memory size but also multibank memory structures to increase the maximum throughput without memory conflict Finally, a low-complexity implementation of an index vector generator is also proposed for our algorithm

On the Fixed-Point Accuracy Analysis of FFT Algorithms

Abstract: In this paper, we investigate the effect of fixed-point arithmetics with limited precision for different fast Fourier transform (FFT) algorithms. A matrix representation of error propagation model is proposed to analyze the rounding effect. An analytic expression of overall quantization loss due to the arithmetic quantization errors is derived to compare the performance with decimation-in-time (DIT) and decimation-in-frequency (DIF) configurations. From the simulation results, the radix-2 DIT FFT algorithm has better accuracy in term of signal-to-quantization-noise ratio (SQNR). Based on the results, a simple criterion of wordlength optimization is proposed to yield comparable accuracy with fewer bit budget.

A fast recursive algorithm for the discrete sine transform

Abstract: A fast recursive algorithm for the discrete sine transform (DST) is developed. An N-point DST can be generated from two identical N/2-point DSTs. Besides being recursive, this algorithm requires fewer multipliers and adders than other DST algorithms. It can be considered as a generalization of the Cooley-Tukey FFT (fast Fourier transform) algorithm. The structure of the algorithm is suitable for VLSI implementation. >

Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing

Abstract: This paper presents an area-efficient algorithm for the pipelined processing of fast Fourier transform (FFT). The proposed algorithm is to decompose a discrete Fourier transform (DFT) into two balanced sub-DFTs in order to minimize the total number of twiddle factors to be stored into tables. The radix in the proposed decomposition is adaptively changed according to the remaining transform length to make the transform lengths of sub-DFTs resulting from the decomposition as close as possible. An 8192-point pipelined FFT processor designed for digital video broadcasting-terrestrial (DVB-T) systems saves 33% of general multipliers and 23% of the total size of twiddle factor tables compared to a conventional pipelined FFT processor based on the radix-22 algorithm. In addition to the decomposition, several implementation techniques are proposed to reduce area, such as a simple index generator of twiddle factor and add/subtract units combined with the two's complement operation