Split-radix FFT algorithm

About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.

A unified expression for split-radix DFT algorithms

Abstract: This paper presents a unified expression that covers all previously reported split-radix-2/2m, where m is an integer larger than one, algorithms. New split-radix algorithms can be also derived from this unified expression. These algorithms flexibly support DFT sizes N = q · 2r, where q is generally an odd integer. Comparisons show that the computational complexity required by the proposed algorithms for the DFT size N = q · 2r is generally not more than that for the DFT size N = 2r. In particular, our examples show that the split-radix-2/4 algorithm requires a smaller computational complexity compared to other split-radix algorithms and the prime factor algorithms.

New radix-3 and −6 decimation-in-frequency fast Hartley transform algorithms

Abstract: Fast algorithms of a transform, like fast Fourier transform (FFT) algorithms, are based on different decomposition techniques. It is shown that these decomposition techniques can also be applied to the computation of the discrete Hartley transform (DHT) for a real-valued sequence. Recently, an efficient decomposition technique for radix-3 decimation-in-time (DIT) FFT and fast Hartley transform (FHT) algorithms has been demonstrated. Such a decomposition technique is implemented for radix-3 and -6 decimation-in-frequency (DIF) FHT algorithms and found to improve the operation count. Efficiency in these algorithms is derived by pairing the rotating factors with an appropriate reordering of the input sequence. From the results, it is seen that the radix-3 and -6 FHT algorithms presented are comparable to the split-radix FHT algorithm in terms of their operation count and will be more efficient when the sequence length is closer to an integer power of the corresponding radix.

Low complexity twiddle factor multiplication with ROM partitioning in FFT processor

Abstract: Proposed is a low-complexity twiddle factor multiplication structure for fast Fourier transform (FFT). In an FFT implementation, the twiddle factor multiplication requires a large ROM to store the twiddle factors. In the proposed structure, the ROM is partitioned into two small ROMs, whose sum of areas is much smaller than that of the original ROM. The proposed structure requires an additional multiplier, but the multiplier is shown to be small in the experimental results. The results show that the proposed structure reduces the area of the twiddle factor multiplication by around 30% with a marginal degradation in SQNR performance.

Acceleration of Perturbation-Based Electric Field Integral Equations Using Fast Fourier Transform

Abstract: In this communication, the computation of the perturbation-based electric field integral equation of the form ${R^{n-1},~n = 0, 1, 2, \ldots ,}$ is accelerated by using fast Fourier transform (FFT) technique. As an effective solution of the low-frequency problem, the perturbation method employs the Taylor expansion of the scalar Green’s function in free space. However, multiple impedance matrices have to be solved at different frequency orders, and the computational cost becomes extremely high, especially for large-scale problems. Since the perturbed kernels still satisfy Toeplitz property on the uniform Cartesian grid, the FFT based on Lagrange interpolation can be well incorporated to accelerate the multiple matrix vector products. Because of the nonsingularity property of high-order kernels when $n\geq 1$ , we do not need to do any near field amendment. Finally, the efficiency of the proposed method is validated in an iterative solver with numerical examples.

A 2048 complex point FFT processor for DAB systems

Abstract: In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result, the proposed structure brings about the 55% chip size reduction compared with the conventional approach.