Split-radix FFT algorithm

About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.

A Grouped Fast Fourier Transform Algorithm Design For Selective Transformed Outputs

Abstract: In this paper, the grouped scheme is specially applied to compute the fast Fourier transform (FFT) when the portions of transformed outputs are calculated selectively. The grouped FFT algorithm applies the scheme of the grouped frequency indices to accelerate the computation of selected DFT outputs. The advantage of the grouped FFT algorithm is that it is more cost-effective than the convenient FFT algorithms when the authors need to compute parts of the transformed outputs, not all outputs. For computing all transformed outputs of the DFT, the computational complexity of the proposed FFT method is less than that of the radix-2 method. Meanwhile, the computational complexity of the proposed fast method approximates to that of the radix-4 FFT algorithm. By sharing coefficients of the twiddle factors in the same frequency group, the grouped FFT can be implemented with hardware sharing VLSI architectures

On pruning the discrete cosine and sine transforms

Abstract: In the paper it is shown that a limited set of output discrete cosine transform (DCT) samples can be computed by a modified real-valued output-pruned FFT algorithm for appropriately permuted data samples. The same is true for the discrete sine transform (DST). Analogously, when computing data contribution from few DCT or DST samples the input-pruned FFT algorithm for inverse FFT can be applied, the input-pruned algorithms for the inverse DCT or DST are obtained. The algorithms are very efficient, their complexities are O(NlogK), where N is the transform size, and K is a divisor of N equal to or greater than the number of computed transform samples, which is less than the number of computed transform samples, which is less than O(NlogN) for the full DCT or DST algorithm. The algorithms are easy to implement, too.

FFT arrays with built-in error correction

Abstract: Fast Fourier transform (FFT) arrays with built-in error correction are proposed. A time shared TMR scheme is used to achieve the error correcting capability. A quarter of the original FFT array is triplicated and voted in each stage. Therefore the hardware complexity of the error correcting FFT array is a little more than 75% of the original FFT array. This is significant since the error correcting design is smaller than the original. The price for this hardware reduction is that the delay time increases by a factor of 4. However, the throughput penalty can be minimized by pipelining. A technology-independent gate-level analysis of hardware complexity and delay time is included. >

Parallel data streams and serial arithmetic for fast Fourier transform processors

Abstract: An algorithm is presented that introduces two degrees of parallelism into the implementation of fast Fourier transform (FFT) processors. That is, both the radix of factorization and the number of arithmetic units may be selected to achieve the required processing speed. A serial vector multiplier that is ideally suited to the implementation of a general radix arithmetic unit is described. It is subsequently shown that a fast Fourier processor having an attractive cost performance ratio can be built by employing serial arithmetic in the implementation of the algorithm developed.

The Hybrid Architecture Parallel Fast Fourier Transform (HAPFFT)

Abstract: THE HYBRID ARCHITECTURE PARALLEL FAST FOURIER