Topic
Split-radix FFT algorithm
About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.
Papers published on a yearly basis
Papers
More filters
Patent•
25 Jan 2010TL;DR: An efficient circuit and method for performing radix-3 Discrete Fourier transform (DFT) of a 3*2M size data frame are provided in this article, where the data frame is split and fast Fourier transformation (FFT) processed as three sub-frames.
Abstract: An efficient circuit and method for performing radix-3 Discrete Fourier transform (DFT) of a 3*2M size data frame are provided. The data frame is split and fast Fourier transform (FFT) processed as three sub-frames. Radix-3 operations are performed on the FFT processed sub-frames over a number of stages with time shared hardware to compute the DFT of the data-frame. FFT operations are performed on the second and third sub-frames to produce respective sub-transforms. Concurrently with FFT processing of the first sub-frame, butterfly operations are performed on the sub-transforms of the second and third sub-frames. Through the use of time-shared hardware and arranging FFT operations to correspond with radix-3 operations at various stages of processing, the DFT is performed with existing FFT processors while reducing resource requirements and/or reducing DFT transform time over the full-parallel radix-3 implementation.
6 citations
20 May 2012
TL;DR: A novel and efficient dynamically partial reconfigurable (DPR) Transform Decomposition (TD) FFT and Radix 2 based IFFT pruning for OFDM based Cognitive Radio on FPGA is presented.
Abstract: Cognitive Radio is an application in which Spectrum utilization can be improved by allowing secondary users to use the spectrum when it is not used by licensed primary users. An adaptive OFDM system for Cognitive radio has the ability to nullify unnecessary individual carriers and avoid interference to licensed primary users. A Fast Fourier Transform (FFT) block forms the core of OFDM design. But, the zero valued inputs outnumber the non-zero valued inputs in the FFT block making the standard FFT algorithms computationally inefficient due to wasted operation on zero values. To overcome this problem, several pruning algorithms have been developed. But many of them are architecturally inefficient for FPGA implementation due to complexity of the overhead operations. Moreover, these algorithms are not suitable for applications like Cognitive radio which has zero inputs in arbitrary distributions making hardware implementation to be complex. This paper presents a novel and efficient dynamically partial reconfigurable (DPR) Transform Decomposition (TD) FFT and Radix 2 based IFFT pruning for OFDM based Cognitive Radio on FPGA. Tested FPGA results on XC2VP30 for the DPR method show the configuration time improvement, good area and power efficiency.
6 citations
17 Dec 2010
TL;DR: A 3780-point FFT algorithm combining of Good-Thomas, Cooley-Tukey, and WFTA algorithm is presented and its hardware implementation by using shift rules based on the analysis of the finite word length effect shows that the output SNR meets the requirement of TDS-OFDM system.
Abstract: In this paper, a 3780-point FFT algorithm combining of Good-Thomas, Cooley-Tukey, and WFTA algorithm is presented and its hardware implementation by using shift rules based on the analysis of the finite word length effect is described. The simulation results show that the output SNR meets the requirement of TDS-OFDM system.
6 citations
01 Jan 2017
TL;DR: The proposed FFT architecture is optimized to support the 802.11ax standard with low latency, area and power requirements, and FPGA implementation results show that the proposed circuit has efficiency 13.7% lower area compared to conventional architecture.
Abstract: Multi-mode fast Fourier Transform (FFT) circuits are essential in orthogonal frequency domain (OFDM) based systems which supports multiple bandwidth. Typically, hardware implementation employs a single FFT circuit for the highest supported bandwidth and using oversampling, the same FFT circuit is used to support lower bandwidth. For the new 802.11ax wireless local area network (WLAN) standard whose frame consists of the regular 3.2us length symbol as well as a longer 12.8us symbol, a fast switchable double-mode FFT circuit is required. In addition, the 802.11ax SIG-B symbol contains a maximum of two independent symbol streams that requires two FFT circuits for the 3.2us symbol length. Our proposed FFT architecture is optimized to support the 802.11ax standard with low latency, area and power requirements. FPGA implementation results show that our proposed circuit has efficiency 13.7% lower area compared to conventional architecture.
6 citations
TL;DR: This paper is part 3 of this series of papers, demonstrates the computation of the PSD (Power Spectral Density) and applications of the DFT and IDFT, which include filtering, windowing, pitch shifting and the spectral analysis of re-sampling.
Abstract: This paper is part 2 in a series of papers about the Discrete Fourier Transform (DFT) and the Inverse Discrete Fourier Transform (IDFT). The focus of this paper is on a fast implementation of the DFT, called the FFT (Fast Fourier Transform) and the IFFT (Inverse Fast Fourier Transform). The implementation is based on a wellknown algorithm, called the Radix 2 FFT, and requires that its’ input data be an integral power of two in length. Part 3 of this series of papers, demonstrates the computation of the PSD (Power Spectral Density) and applications of the DFT and IDFT. The applications include filtering, windowing, pitch shifting and the spectral analysis of re-sampling.
6 citations