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Split-radix FFT algorithm
About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.
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Journal Article•
TL;DR: An improved algorithm with high accuracy is proposed based on the attenuation characteristics of the Hanning-windowed discrete spectrum of signal, which reduces the spectral leakage further, and then the interpolation is applied to derive the practical correction formulas of the harmonic frequency, amplitude and phase.
Abstract: Due to the wide use of non-linear components, harmonic problem becomes increasingly serious It is difficult to perform accurate harmonic analysis with fast Fourier transform (FFT) under the unsynchronized sampling conditions Windowed interpolation methods can improve the accuracy of FFT for harmonic analysis An improved algorithm with high accuracy is proposed based on the attenuation characteristics of the Hanning-windowed discrete spectrum of signal Via a specific polynomial transform of the spectral sequence, the algorithm reduces the spectral leakage further, and then the interpolation is applied to derive the practical correction formulas of the harmonic frequency, amplitude and phase Comparison with Hanning and Blackman-Harris interpolation FFT methods is carried out by Matlab simulations, which verifies the higher analysis accuracy of the proposed algorithm An experiment on capacitor harmonic current demonstrates its validity further
6 citations
26 May 2013
TL;DR: The proposed lifting based FFT (L-FFT) based on fast Hartley transform (FHT) has a simpler structure than existing ones because fewer lifting steps need to be approximated and requires fewer memories for the internal implementation than the conventional FFTs.
Abstract: The multiplierless fast Fourier transform (FFT) with dyadic-valued (rational) coefficients is important for many signal processing tools. The proposed lifting based FFT (L-FFT) based on fast Hartley transform (FHT) has a simpler structure than existing ones because fewer lifting steps need to be approximated. In addition, it has a structure of real-valued calculation followed by complex-valued parts, thereby it requires fewer memories for the internal implementation than the conventional FFTs.
6 citations
01 Dec 2014
TL;DR: The proposed architecture consists of cascaded multiplier-less cells, and each cell stage performs partial twiddle factor multiplications with low-complexity adders and multiplexers, and is suitable for either pipelined or memory based FFT architectures.
Abstract: This paper presents new rotator architecture for FFT computation. The proposed architecture consists of cascaded multiplier-less cells, and each cell stage performs partial twiddle factor multiplications with low-complexity adders and multiplexers. Besides, for further area reduction, each cell is optimized with the technique of common subexpression sharing. Since those twiddle factors involved in computation are realized with multipliers generated on-the-fly by a scheme of coefficient selection, the proposed architecture doesn't require memory space to store any twiddle factors. Variable FFT lengths ranging from 64 ∼ 32768 points can be supported by flexibly adding or removing some cell stages, depends on FFT length. Compared to CORDIC-based architectures, the proposed architecture has lower latency. The implementation results show that the proposed architecture is area-efficient and is suitable for either pipelined or memory based FFT architectures.
6 citations
TL;DR: A multiddimensional fast-Fourier-transform algorithm is developed for the computation of multidimensional Fourier and Fourier-like discrete transforms; it has considerably less multiplications than the conventional fast-fourier -transform methods.
Abstract: A multidimensional fast-Fourier-transform algorithm is developed for the computation of multidimensional Fourier and Fourier-like discrete transforms; it has considerably less multiplications than the conventional fast-Fourier-transform methods.
6 citations
Patent•
19 Aug 2009TL;DR: An FFT/IFFT apparatus and method are provided in this article, where the storage unit has as many addresses as the number of bits of input data, and a storage unit consists of a first FFT unit, a second FFT-IFFT unit and a third FFT and IFT-IFT unit.
Abstract: An FFT/IFFT apparatus and method are provided. The FFT/IFFT apparatus includes a storage unit, a first FFT/IFFT unit, a second FFT/IFFT unit, and a third FFT/IFFT unit. The storage unit has as many addresses as the number of bits of input data. The first FFT/IFFT unit sequentially stores half of the input data in the storage unit, performs a first-point FFT/IFFT operation while sequentially receiving the other half of the input data, and stores the first-point FFT/IFFT operation result in the storage unit. The second FFT/IFFT unit performs a second-point FFT/IFFT operation on the first-point FFT/IFFTed data, and stores the second-point FFT/IFFT operation result in the storage unit. The third FFT/IFFT unit performs a third-point FFT/IFFT operation on the second-point FFT/IFFTed data, and stores the third-point FFT/IFFT operation result in the storage unit.
6 citations