Split-radix FFT algorithm

About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.

Fast algorithms for computing the discrete cosine transform

Abstract: Efficient methods for mapping odd-length type-II, type-II, and type-IV DCTS to a real-valued DFT are presented. It is found that odd-length type-II and type-III DCTs can be transformed, by means of an index mapping, to a real-valued DFT of the same length using permutations and sign changes only. The real-valued DFT can then be computed by efficient real-valued FFT algorithms such as the prime factor algorithm. Similar mapping is introduced to convert a type-IV DCT to a real-valued DFT up to a scaling factor and some additions. Methods for computing DCTs with even lengths are also discussed. >

A High-Speed FFT Processor

Abstract: A high-speed, low-power, fast Fourier transform (FFT) processor is described in this paper. The FFT processor is designed around parallel arithmetic functions (16 by 16 multiplier and 16-bit adders) and can operate up to a 17.0-MHz clock rate. It performs a 128-point FFT in 250 μs at 16-MHz clock rate and therefore can be used for applications such as frequency-division multiplexing/timedivision multiplexing (FDM/TDM) transmultiplexer. The processor was designed and tested according to the design specifications. Its standalone feature permits its use in a variety of systems employing spectral analysis. The high-speed requirements are met by a real-time address generation scheme. The design can be used for a higher order FFT by providing extra memory space.

An In-Place FFT Architecture for Real-Valued Signals

Abstract: This brief presents a novel scalable architecture for in-place fast Fourier transform (IFFT) computation for real-valued signals. The proposed computation is based on a modified radix-2 algorithm, which removes the redundant operations from the flow graph. A new processing element (PE) is proposed using two radix-2 butterflies that can process four inputs in parallel. A novel conflict-free memory-addressing scheme is proposed to ensure the continuous operation of the FFT processor. Furthermore, the addressing scheme is extended to support multiple parallel PEs. The proposed real-FFT processor simultaneously requires fewer computation cycles and lower hardware cost compared to prior work. For example, the proposed design with two PEs reduces the computation cycles by a factor of 2 for a 256-point real fast Fourier transform (RFFT) compared to a prior work while maintaining a lower hardware complexity. The number of computation cycles is reduced proportionately with the increase in the number of PEs.

A fast algorithm for the Fourier transform over finite fields and its VLSI implementation

Abstract: The Fourier transform over finite fields is mainly required in the encoding and decoding of Reed-Solomon and BCH codes. An algorithm for computing the Fourier transform over any finite field GF(p/sup m/) is introduced. It requires only O(n(log n)/sup 2//4) additions and the same number of multiplications for an n-point transform and allows in some fields a further reduction of the number of multiplications to O(n log n). Because of its highly regular structure, this algorithm can be easily implementation by VLSI technology. >

Split vector-radix fast Fourier transform

Abstract: The split-radix approach for computing the discrete Fourier transform (DFT) is extended for the vector-radix fast Fourier transform (FFT) to two and higher dimensions. It is obtained by further splitting the (N/2*N/2) transforms with twiddle factors in the radix (2*2) FFT algorithm. The generalization of this split vector-radix FFT algorithm to higher radices and higher dimensions is also presented. By introducing a general approach for constructing the fast Hartley transform (FHT) from the corresponding FFT, new vector- and split-vector-radix FHT algorithms with the same desirable properties as their FFT counterparts are obtained. >