Split-radix FFT algorithm

About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.

A new FFT algorithm of radix 3,6, and 12

Abstract: A new algorithm for implementation of radix 3, 6, and 12 FFT is introduced. An FFT using this algorithm is computed in an ordinary (1,j) complex plane and the number of additions can be significantly reduced; the number of multiplication is also reduced. High efficiency of the algorithm is derived from the fact that, if an input sequence is favorably reordered, rotating factors can be treated in pairs so that the rotating factors are conjugate to each other.

Arrayable modular FFT processor

Abstract: A modular, arrayable, FFT processor for performing a preselected N-point FFT algorithms. The processor uses an input memory to receive and store data from a plurality of signal-input lines, and to store intermediate butterfly results. At least one Direct Fourier Transformation (DFT) element selectively performs R-point direct Fourier transformations on the stored data according to a the FFT algorithm. Arithmetic logic elements connected in series with the DFT stage perform required phase adjustment multiplications and accumulate complex data and multiplication products for transformation summations. Accumulated products and summations are transferred to the input memory for storage as intermediate butterfly results, or to an output memory for transfer to a plurality of output lines. At least one adjusted twiddle-factor storage element provides phase adjusting twiddle-factor coefficients for implementation of the FFT algorithm. The coefficients are preselected according to a desired size for the Fourier transformation and a relative array position of the arrayable FFT processor in an array of processors. The adjusted twiddle-factor coefficients are those required to compute all mixed power-of-two, power-of-three, power-of-four, and power-of-six FFTs up to a predetermined maximum-size FFT point value for the array which is equal to or greater than N.

Implementation of FFT structures using the residue number system

Abstract: This paper considers the implementation of a fast Fourier transform (FFT) structure using arrays of read-only memories. The arithmetic operations are based entirely on the residue number system. The most important aspect of the structure relates to the scaling arrays, which are required to prevent overflow. Because of the limitations of the number system, scaling factors have to be chosen on an a priori basis. This paper develops optimum procedures for choosing both scaling factors and the position of scaling arrays in the structure. Some examples are presented relating to the filtering of speech via a convolutional filter structure.

Moving discrete Fourier transform

Abstract: A common approach to signal or image processing using the discrete Fourier transform (DFT) is to extract a portion of the signal by windowing, and then to form the DFT of the window contents. By moving the window appropriately, the entire signal may be covered. The moving fast Fourier transform (MFFT) algorithms developed in the paper apply to the particular case where the window is moved one data point along the signal between successive transforms. The MFFT ‘updates’ the DFT to reflect the new window contents, using less computation than in directly evaluating the new transform with the FFT algorithm. The MFFT has computational order Nin 1 — d and N2in 2 — d, a factor of log2Nimprovement over the FFT. MFFT algorithms are derived for use with the boxcar, split-triangular, Hanning, Hamming and Blackman windows. Generalisation to piecewise linear and piecewise polynomial windows is discussed.

Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

Abstract: In this paper, we propose a hardware-efficient mixed generalized high-radix (GHR) reconfigurable fast Fourier transform (FFT) processor for long-term evolution applications. The GHR processor based on radix-25/16/9 uses a 2-D factorization scheme as the high-radix unit and a 1-D factorization method as the system data routing technology. The 2-D factorization scheme is implemented by an enhanced delay element matrix structure, which supports 25-, 16-, 9-, 8-, 5-, 4-, 3-, and 2-point FFTs. Two different designs were implemented. One design (called discrete Fourier transform core) supports 34 different transform sizes from 12 to 1296 points, while the other design (called FFT core) supports five different power-of-two sizes from 128 to 2048 points. The 1-D factorization method is performed by a coprime accessing technology, which accesses the data in parallel without conflict using a RAM. The GHR combines 2-D and 1-D factorization techniques and improves the throughput by a factor of two to four with comparable hardware cost compared with the previous designs. The speed–area ratio of the proposed scheme is nearly two times better than that of previous FFT processors. Application-specified integrated circuit implementation results based on a 0.18- $\mu{\rm m}$ technology are also provided.