Topic
Split-radix FFT algorithm
About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.
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07 Jun 2009
TL;DR: An efficient addressing scheme for radix-4 FFT processor that avoids the modulo-r addition in the address generation and the critical path is independent from the FFT transform length N, making it extremely efficient for large FFT transforms.
Abstract: In this study, an efficient addressing scheme for radix-4 FFT processor is presented. The proposed method uses extra registers to buffer and reorder the data inputs of the butterfly unit. It avoids the modulo-r addition in the address generation; hence, the critical path is significantly shorter than the conventional radix-4 FFT implementations. A significant property of the proposed method is that the critical path of the address generator is independent from the FFT transform length N, making it extremely efficient for large FFT transforms. For performance evaluation, the new FFT architecture has been implemented by FPGA (Altera Stratix) hardware and also synthesized by CMOS 0.18µm technology. The results confirm the speed and area advantages for large FFTs. Although only radix-4 FFT address generation is presented in the paper, it can be used for higher radix FFT.
21 citations
TL;DR: A high-performance parallel three-dimensional fast Fourier transform (FFT) algorithm on clusters of PCs is proposed and it is shown that the block three- dimensional FFT algorithm improves performance by utilizing the cache memory effectively.
21 citations
TL;DR: A new parallel FFT algorithm is proposed that removes the complex multiplier between the two pipeline stages and simplifies the address generation of twiddle factors and reduces the number of twiddles to a minimum.
Abstract: Usually, parallel pipelined FFT processors are used to compute long FFTs due to high processing rate and easy implementation. The efficient VLSI implementation of each FFT processor at the pipelines is a critical problem to be considered. We propose a new parallel FFT algorithm that removes the complex multiplier between the two pipeline stages. The new algorithm also simplifies the address generation of twiddle factors and reduces the number of twiddle factors to a minimum. With the new algorithm, each FFT processor at the pipelines can be integrated easily onto a single chip.
21 citations
01 Jan 2001
TL;DR: The leakage of FFT is discussed briefly and the interpolation algorithm on Blackman Harris window is analyzed in detail, showing that the improved algorithm holds a very high precision when used for the unsynchronized sample sequence.
Abstract: The FFT has a higher error when used with a sample sequence which is not synchronized with the signal,which makes that the electric harmonic parameters can not be gotten accurately.To reduce the influence of an unsynchronized sample sequence on FFT and to improve the precision of harmonics in electric machine testing, This paper improves the algorithm by using windows and interpolation methods.This paper first discusses the leakage of FFT briefly and then analyzes the interpolation algorithm on Blackman Harris window in detail. With the new algorithm,we can get the accurate frequency offset and other accurate harmonic parameters by solving high order interpolation equation with the help of MATLAB language.After this,we make a little change to the interpolation formula,which can make the calculating accuracy be further improved on every condition especially for the severe leakage.An example of simulation is given and validates that the improved algorithm holds a very high precision when used for the unsynchronized sample sequence.
21 citations
05 Dec 2005
TL;DR: A new general method to deduce FFT algorithms is introduced, and the deduced second radix-2 decimation-in-time FFT algorithm is transformed into another parallelizable sequential form, reducing the time complexity of DFT to O(nlogn/p) (where p is the number of processors).
Abstract: Discrete Fourier transform (DFT) has many applications in digital signal and image processing and other scientific and technological domains, but its time complexity of direct computation is O(n2), limiting greatly its application range. Thus many people have developed fast Fourier transform (FFT) algorithms, reducing the complexity from O(n2) to O(nlogn)(In this paper logn denotes log2n).But for large n, O(nlogn) is still very high. So multiprocessor systems have been used to speed up the computation of DFT. This paper first introduces a new general method to deduce FFT algorithms, then transforms the deduced second radix-2 decimation-in-time FFT algorithm into another parallelizable sequential form, and finally transforms the latter algorithm into a new parallel FFT algorithm, reducing the time complexity of DFT to O(nlogn/p) (where p is the number of processors). Using similar methods, the authors can also design other new parallel 1-D and 2-D FFT algorithms.
21 citations