Split-radix FFT algorithm

About: Split-radix FFT algorithm is a research topic. Over the lifetime, 1845 publications have been published within this topic receiving 41398 citations.

Fast parallel implementation of DFT using configurable devices

Abstract: In this paper we propose a fast parallel implementation of Discrete Fourier Transform (DFT) using FPGAs. Our design is based on the Arithmetic Fourier Transform (AFT) using zero-order interpolation. For a given problem of size N, AFT requires only O(N2) additions and O(N) real multiplications with constant factors. Our design employes 2p + 1 PEs (1 ≤ p ≤ N), O(N) memory and fixed 1/O with the host. It is scalable over p (1 ≤ p ≤ N) and can solve larger problems with the same hardware by increasing the memory. All the PEs have fixed architecture. Our implementation is faster than most standard DSP designs for FFT. It also outperforms other FPGA-based implementations for FFT, in terms of speed and adaptability to larger problems.

SIMD Vectorization of Non-Two-Power Sized FFTs

Abstract: SIMD (single instruction multiple data) vector instructions, such as Intel's SSE family, are available on most architectures, but are difficult to exploit for speed-up. In many cases, such as the fast Fourier transform (FFT), signal processing algorithms have to undergo major transformations to map efficiently. Using the Kronecker product formalism, we rigorously derive a novel variant of the general-radix Cooley-Tukey FFT that is structured to map efficiently for any vector length v and radix. Then, we include the new FFT into the program generator spiral to generate actual C implementations. Benchmarks on Intel's SSE show that the new algorithms perform better on practically all sizes than the best available libraries Intel's MKL and FFTW.

4k-point FFT algorithms based on optimized twiddle factor multiplication for FPGAs

Abstract: In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays(FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.

Basefield transforms with the convolution property

Abstract: We present a general framework for constructing transforms in the field of the input which have a convolution-like property. The construction is carried out over the reals, but is shown to be valid over more general fields. We show that these basefield transforms can be viewed as "projections" of the discrete Fourier transform (DFT). Furthermore, by imposing an additional condition on the projections, one may obtain self-inverse versions of the basefield transforms. Applying the theory to the real and complex fields, we show that the projection of the complex DFT results in the discrete combinational Fourier transform (DCFT) and that the imposition of the self-inverse condition on the DCFT yields the discrete Hartley transform (DHT). Additionally, we show that the method of projection may be used to derive efficient basefield transform algorithms by projecting standard FFT algorithms from the extension field to the basefield. Using such an approach, we show that many of the existing real Hartley algorithms are projections of well-known FFT algorithms. >