Spurious-free dynamic range

About: Spurious-free dynamic range is a research topic. Over the lifetime, 2483 publications have been published within this topic receiving 27058 citations.

A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/

Abstract: A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from DC to Nyquist. The measured differential nonlinearity and integral nonlinearity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-/spl mu/m, single-poly, four-metal, 3.3 V, standard digital CMOS process and occupies 0.6 mm/sup 2/. When operating at 500 MSample/s, it dissipates 125 mW from a 3.3 V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry.

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

Abstract: In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than /spl plusmn/0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-/spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

Radio Over Fiber for Picocellular Network Architectures

Abstract: We have studied RF transmission over various multimode fibers (MMFs) and a standard single-mode fiber, targeting picocellular networks for voice, data, and video applications. Bandwidth requirements of MMF links that are based on vertical-cavity surface-emitting laser (VCSEL) have been extensively studied. The performance of the radio-over-fiber link is assessed in terms of the error vector magnitude. Also conducted was a full system analysis, including the investigation of an achievable dynamic range and a noise figure for different low-cost architectures. This was compared to coax-based RF transmission. The IEEE 802.11 a/b/g standard, as well as other applications like radio frequency identification tracking, was considered. For experimental investigations, we have used both commercial wireless access points and a vector signal generator as a signal source, with two types of directly modulated VCSELs - 850-nm sources and 1310-nm high-speed uncooled single-mode AlGaInAs/InP VCSELs. A robust system performance was demonstrated in both 2.4- and 5-GHz RF bands, and record multimode and standard single-mode fiber transmission distances were achieved. A transponder design that can meet system requirements in terms of sensitivity ( 95 dBldrHz2/3) for a dual-band wireless LAN (WLAN) fiber-radio picocellular network was developed. A full 14-cell experimental WLAN system with cells of 4-m radius was implemented to study networking issues such as handoff and cochannel interference.

A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input

Abstract: This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-/spl mu/m double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm/sup 2/ ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V.

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

Abstract: A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.