About: Spy-Bi-Wire is a(n) research topic. Over the lifetime, 64 publication(s) have been published within this topic receiving 773 citation(s).
Papers published on a yearly basis
TL;DR: This paper describes how to use JTAG (JTAG: Joint Test Action Group, also called boundary-scan) for producing a forensic image (image: an one-on-one copy of data found on an exhibit) of an embedded system.
Abstract: This paper describes how to use JTAG (JTAG: Joint Test Action Group, also called boundary-scan) for producing a forensic image (image: an one-on-one copy of data found on an exhibit) of an embedded system. A JTAG test access port is normally used for testing printed circuit boards or for debugging embedded software. The method described in this paper uses a JTAG test access port to access memory chips directly. By accessing memory chips directly, the risk of changing data in the exhibit is minimized. Also user level passwords can be omitted.
•20 Jul 1995
Abstract: A system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG protocol or the non-compliant device. A specialized Test Access Port Controller controls and monitors the states applied to the non-compliant device in order to eliminate the PAUSE state in the non-compliant device and to limit the Run-Test/Idle state to one clock period.
13 Jun 2010
TL;DR: An anti-tamper JTAG Tap design which uses SHA256 secure hash and a true random number generator (TRNG) to create a low gate overhead challenge/response based access system for IC test and on-chip internals is described.
Abstract: This paper describes an anti-tamper JTAG Tap design which uses SHA256 secure hash and a true random number generator (TRNG) to create a low gate overhead challenge/response based access system for IC test and on-chip internals. The system may be used to enable 1149.1 TAP instructions or may control access to an IEEE P1687 on-chip instrument. The TAP owner (manufacturer of the IC) may then use DRM (Digital Rights Management) based JTAG software to manage which end users have access to the TAP or TAP accessible areas of the IC.
•30 Oct 1998
Abstract: An apparatus capable of testing a plurality of JTAG compliant integrated circuits where at least one of the integrated circuits includes an enhanced embedded debug module is described. The apparatus is capable of selectively testing certain of the integrated circuits located at specified locations. In this way, integrated circuits included in a target device having defective or missing integrated circuits can still be tested. The apparatus also allows access to enhanced JTAG debug protocol within a mixed IC (OCDS and non-OCDS) network.
•10 Jun 2003
Abstract: An integrated circuit for a smart card may include a transceiver for communicating with a host device and a Joint Test Action Group (JTAG) test controller for performing at least one test operation. Further, the integrated circuit may also include a processor for causing the JTAG test controller to initiate the at least one test operation based upon receiving at least one test request from the host device via the transceiver. More particularly, the processor may convert the at least one test request to JTAG data for the JTAG test controller. That is, the integrated circuit advantageously allows communications between the host device and the JTAG controller via a system bus, for example, without the need for a dedicated JTAG test access port (TAP) which is typically required for accessing JTAG controllers.