Showing papers on "Spy-Bi-Wire published in 2008"

Use of JTAG boundary-scan for testing electronic circuit boards and systems

Abstract: Todaypsilas complex printed circuit boards and high-density ball-grid array and other chip-size package ICs have led to the standardization and wide-spread use of JTAG (Joint Test Action Group) boundary-scan technology for test and debug. Topics include the evolution of JTAG standards, basic fundamentals of boundary-scan architecture, board testability using boundary-scan and system-level testing. Additionally, this paper will address the advantages and disadvantages of JTAG testing and propose advanced JTAG test methodologies including remote testing and diagnostics.

Design and Implementation of a Single-Chip ARM-Based USB Interface JTAG Emulator

Abstract: Boundary-scan technology is a popular design-for-test technology, which is used by some embedded chips by means of embedding special boundary scan cells inside the circuits. It allows the debugger to talk via a JTAG port directly to the IC's core. As more and more chips using the JTAG interface, the application of JTAG emulator becomes frequent. Commercial JTAG emulators using parallel port on the market are usually expensive and inconvenience. This paper describes two methods to design an inexpensive USB interface JTAG emulator based on a single-chip ARM, including theirs hardware and software. One is the GPIO pins of an ARM device are used to generate TAP timing and its USB port is used to communicate with PC. Another is used the SPI interface to generate higher TCK. Result shows that this emulator not only has high speed but also is portable.

Debug port controller architectures for system-on-chip integrated circuits

Abstract: Since its introduction, test access port has become an inseparable part of the majority of integrated circuits. Commonly referred to as JTAG, it meant to provide a solution to the problem of testing assembled printed circuit boards as well as a means of accessing and controlling on-chip test-dedicated features. With appearance and ever increasing complexity of multi-processor system-on-chip integrated circuits, the architectural variety and intended roles of JTAG based test features significantly expanded. Observability and controllability of an integrated circuitpsilas functionality for debug and test, security protection, power management, clocking schemes management is only a partial list of the features a JTAG based test and debug controller supports in a modern system-on-chip. This paper presents a categorization and analysis of debug port controller architectures and their key features for use in system-on-chip integrated circuits.

Asynchronous communication apparatus using JTAG test data registers

Abstract: An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, the present apparatus is for extending the IEEE 1149.1 JTAG standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry. The apparatus includes an integrated circuit having function register and JTAG standard TDR. Digital logic is configured to control the direct transfer of data between the JTAG standard TDR and the function register.

Testing technology research on Jtag and network communications

Abstract: In order to extend the application of the testing technology based on Jtag bus,this paper introduces a project designing with Jtag bus and Ethernet interlinked with each other.By analyzing the network model and the realization of the protocol conversion,this paper discusses the principles of connection between Jtag bus and Ethernet,and also builds a fundamental structure of the experimentation.It is exerted a experimental tested verification to a chip with this technology.The experimental result is analyzed and indicated that the design of this system absolutely has a good feasibility.This technology,with its high practicability,is another extended application of the boundary-scanning technology used in the area of testability.

Research of Embedded Debug Based on JTAG

Abstract: The theory of debugging an embedded processor through JTAG based on ARM7TDMI is describedThe efficiency of downloading program with JTAG is analyzedA general downloading algorithm of high performance is put forward for ARM