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Showing papers on "Spy-Bi-Wire published in 2012"


Journal ArticleDOI
TL;DR: The standard JTAG Architecture with enhanced security mechanism is described using VHDL and hence prevents the unauthorized users from accessing the private and confidential information of a device.
Abstract: For in–circuit testing and debugging JTAG (Joint Test Access Group) is one of the most powerful standard architecture of DFT (Design For Testability). But JTAG can also act as a tool for hacking and hence makes the devices vulnerable for attacks. This paper presents a Security mechanism for JTAG and hence prevents the unauthorized users from accessing the private and confidential information of a device. This method is highly compatible with the IEEE 1149.1 standard and requires no modification in the Intellectual Property of an IC. In this paper the standard JTAG Architecture with enhanced security mechanism is described using VHDL.

6 citations


Patent
Lee D. Whetsel1
05 Jun 2012
TL;DR: In this article, the authors describe a process and apparatus for accessing devices on a substrate using a single interface between the substrate and a JTAG controller, which can be either wired or wireless.
Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( 504 ), only reduced pin JTAG devices ( 506 ), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface ( 502 ) between the substrate ( 408 ) and a JTAG controller ( 404 ). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Journal ArticleDOI
TL;DR: The presented package includes a software environment Trainer 1149 that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process and is the main component of a recent goJTAG initiative that aims at bringing JTAG tools closer to the user.
Abstract: This paper presents a software/hardware bundle for studying, training and research related to IEEE 1149.1 Boundary Scan (BS) standard. The presented package includes a software environment Trainer 1149 that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process. Trainer 1149 provides a cozy graphical design and simulation environment of BS-enabled chips and non-BS clusters. It provides the user with a full flexibility in working with any type of BS structures by supporting standard formats such as Boundary Scan Description Language and SVF (for defining test patterns). A special fault simulation mode allows injecting various types of interconnection faults to simulate their impact and inspect them using interactive tools. Trainer 1149 is the main component of a recent goJTAG initiative that aims at bringing JTAG tools closer to the user for both learning and experimental work purposes. The software part is implemented in multi-platform Java environment and distributed as an open-source freeware. Using a convenient low-cost USB-JTAG controller, one can also test real defects in real hardware. Such combination of features is unique for a public domain BS package. Keywords—JTAG, boundary scan, IEEE 1149.1, Trainer 1149, goJTAG.