Topic
Spy-Bi-Wire
About: Spy-Bi-Wire is a research topic. Over the lifetime, 64 publications have been published within this topic receiving 773 citations.
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Patent•
24 Jan 2011TL;DR: In this paper, an optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit, which can be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and trace operations.
Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.
01 Jan 2011
TL;DR: The JTAG (Boundary Scan Architecture IEEE 1149.1) is reviewed and an application designed to allow programming a Spostan II FPGA is shown.
Abstract: The JTAG (Boundary Scan Architecture IEEE 1149.1), is an efficient architecture that facilitates debugging and performance testing for digital devices. Nowadays this architecture is used by many manufacturers in the programming, and emulation of microcontrollers, FPGAs and microprocessors based systems. This article reviews the main technical aspects of this standard and shows an application designed to allow programming a Spostan II FPGA
Patent•
05 Jun 2012TL;DR: In this article, the authors describe a process and apparatus for accessing devices on a substrate using a single interface between the substrate and a JTAG controller, which can be either wired or wireless.
Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( 504 ), only reduced pin JTAG devices ( 506 ), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface ( 502 ) between the substrate ( 408 ) and a JTAG controller ( 404 ). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
TL;DR: The presented package includes a software environment Trainer 1149 that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process and is the main component of a recent goJTAG initiative that aims at bringing JTAG tools closer to the user.
Abstract: This paper presents a software/hardware bundle for studying, training and research related to IEEE 1149.1 Boundary Scan (BS) standard. The presented package includes a software environment Trainer 1149 that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process. Trainer 1149 provides a cozy graphical design and simulation environment of BS-enabled chips and non-BS clusters. It provides the user with a full flexibility in working with any type of BS structures by supporting standard formats such as Boundary Scan Description Language and SVF (for defining test patterns). A special fault simulation mode allows injecting various types of interconnection faults to simulate their impact and inspect them using interactive tools. Trainer 1149 is the main component of a recent goJTAG initiative that aims at bringing JTAG tools closer to the user for both learning and experimental work purposes. The software part is implemented in multi-platform Java environment and distributed as an open-source freeware. Using a convenient low-cost USB-JTAG controller, one can also test real defects in real hardware. Such combination of features is unique for a public domain BS package. Keywords—JTAG, boundary scan, IEEE 1149.1, Trainer 1149, goJTAG.
01 Jan 1995
TL;DR: This application report describes the design and implementation of a hardware monitor that provides information from the processor level up to the application level using the on-chip analysis module of the Texas Instruments (TI) TMS320C40 digital signal processor (DSP) and a boundary-scan technique according to the IEEE 1149.1 JTAG-standard.
Abstract: This application report describes the design and implementation of a hardware monitor that provides information from the processor level up to the application level. It uses the on-chip analysis module of the Texas Instruments (TI) TMS320C40 digital signal processor (DSP) and a boundary-scan technique according to the IEEE 1149.1 JTAG-standard. The monitor can be used for both single processor and multiprocessor systems. There is no limit on the number of processors monitored. An instrumentation of the software running on the DSPs is not required. The monitor influences the application in terms of runtime but does not change the order of events. This document was an entry in the 1995 DSP Solutions Challenge, an annual contest organized by TI to encourage students from around the world to find innovative ways to use DSPs. For more information on the TI DSP Solutions Challenge, see TI’s World Wide Web site at www.ti.com.