Topic
Spy-Bi-Wire
About: Spy-Bi-Wire is a research topic. Over the lifetime, 64 publications have been published within this topic receiving 773 citations.
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Patent•
01 Oct 2011TL;DR: In this paper, the authors present an approach for performing JTAG testing on production devices and systems through industry standard interfaces such as a USB or Ethernet port and a bus and/or interconnect over which test input and result data is transferred via the standard communication interface.
Abstract: Apparatus and techniques for performing JTAG testing on production devices and systems through industry standard interfaces The devices employ processors configured to receive packetized test input data from a tester over a standard communication interface such as a USB or Ethernet port and perform associated testing operations defined by the test input data, such as JTAG-compliant testing This is facilitated, in part, via use of a bridge and one or more DFx handlers, with the bridge operating as an interface between the DFx handlers and a bus and/or interconnect over which test input and result data is transferred via the standard communication interface The techniques enable testing such as JTAG testing to be performed on fully-assembled devices and systems without requiring the use of dedicated test or debug ports
11 citations
Patent•
ZTE1
TL;DR: In this article, a Joint Test Action Group (JTAG) apparatus and a method for implementing JTAG data transmission are disclosed, which includes an isolation circuit connected with a processor and pins of a JTAG programmable logic device.
Abstract: A Joint Test Action Group (JTAG) apparatus and a method for implementing JTAG data transmission are disclosed. The JTAG apparatus includes an isolation circuit connected with a processor and pins of a JTAG programmable logic device, wherein the isolation circuit has a register/registers corresponding to the pins of the JTAG programmable logic device. Based on a high or low level signal written into the register/registers of the isolation circuit by the processor, the isolation circuit drives the pins of the JTAG programmable logic device, and transmits the JTAG data corresponding to the high or low level signal from the processor to the JTAG programmable logic device. The isolation circuit is used to implement protection of a JTAG interface or a serial port of a personal computer connected with the JTAG apparatus.
9 citations
06 Oct 2008
TL;DR: Two methods to design an inexpensive USB interface JTAG emulator based on a single-chip ARM, including theirs hardware and software are described, which not only has high speed but also is portable.
Abstract: Boundary-scan technology is a popular design-for-test technology, which is used by some embedded chips by means of embedding special boundary scan cells inside the circuits. It allows the debugger to talk via a JTAG port directly to the IC's core. As more and more chips using the JTAG interface, the application of JTAG emulator becomes frequent. Commercial JTAG emulators using parallel port on the market are usually expensive and inconvenience. This paper describes two methods to design an inexpensive USB interface JTAG emulator based on a single-chip ARM, including theirs hardware and software. One is the GPIO pins of an ARM device are used to generate TAP timing and its USB port is used to communicate with PC. Another is used the SPI interface to generate higher TCK. Result shows that this emulator not only has high speed but also is portable.
8 citations
25 Jul 2009
TL;DR: With the enhanced features, all test functions including stuck-at scan, at-speed scan, memory BIST and high-speed physical layer tests can be controlled by the J TAG controller besides traditional boundary scan tests, and further on-chip debug features are also integrated in this enhanced JTAG controller.
Abstract: Based on one complex SOC chip, one functional enhancement methodology to standard IEEE P1149.1 JTAG controller is proposed in this paper. With the enhanced features, all test functions including stuck-at scan, at-speed scan, memory BIST and high-speed physical layer tests can be controlled by the JTAG controller besides traditional boundary scan tests, and further on-chip debug features are also integrated in this enhanced JTAG controller. Therefore, the chip costs can be reduced, and the software development and debug can be facilitated with the enhanced JTAG controller.
8 citations
Patent•
11 Jan 2001
TL;DR: In this article, a method for activating a microprocessor, which is part of a microcontroller, within the framework of a boundary scan test procedure according to IEEE standard 1149, using a Joint European Test Action Group (JTAG) interface of the microprocessor.
Abstract: A method for activating a microprocessor, which is part of a microcontroller, within the framework of a boundary scan test procedure according to Institute of Electrical and Electronic Engineers (IEEE) standard 1149, using a Joint European Test Action Group (JTAG) interface of the microprocessor. To be able to test a microcontroller, using the boundary scan test procedure, even when the JTAG interface is not accessible by a separate hardware adaptor of a JTAG tester, it is proposed that the JTAG interface of the microprocessor be activated by a test routine executable on the microprocessor.
8 citations