Spy-Bi-Wire

About: Spy-Bi-Wire is a research topic. Over the lifetime, 64 publications have been published within this topic receiving 773 citations.

PXI Express Based JTAG / Boundary Scan ATE for Structural Board and System Test

Abstract: Being well established as a valuable test and debug access methodology in the commercial electronics business, JTAG/ boundary scan as defined in IEEE Std. 1149.1 continues to advance into government and military applications as well. This test technology can be implemented in test systems based on various hardware platforms. This paper presents benefits a high speed tester platform such as PXI express provides for structural test and in-system programming applications based on JTAG / boundary scan access.

Design of Structure of Debugging Software in CPU Based on JTAG

Abstract: It is important to own the capability of debugging application and system software and multitasking system in the design of microprocessor at present. In this paper, we proposed a debugging structure based on JTAG port and combined with boundary-scan technology and interrupt system, which can allow users to debug software procedure by the debugger which is connected to JTAG port. It is easy to form a standardized structure and applicable to all general-purpose CPU and only increases the difficulty of the circuit logic design.

Debug port controller architectures for system-on-chip integrated circuits

Abstract: Since its introduction, test access port has become an inseparable part of the majority of integrated circuits. Commonly referred to as JTAG, it meant to provide a solution to the problem of testing assembled printed circuit boards as well as a means of accessing and controlling on-chip test-dedicated features. With appearance and ever increasing complexity of multi-processor system-on-chip integrated circuits, the architectural variety and intended roles of JTAG based test features significantly expanded. Observability and controllability of an integrated circuitpsilas functionality for debug and test, security protection, power management, clocking schemes management is only a partial list of the features a JTAG based test and debug controller supports in a modern system-on-chip. This paper presents a categorization and analysis of debug port controller architectures and their key features for use in system-on-chip integrated circuits.

IEEE-1149.1 use in design for verification and testability at Texas Instruments

Abstract: Products aimed at standardization and cost reduction of IC and system test and debug, compatible with the JTAG/IEEE-1149.1 scan protocols and standards, are discussed. Included are ASIC (application-specific integrated circuit) cells, standard interface ICs, a bus master IC, a controller interface board for IBM compatibles, a high-speed scan interface, and software to control the scan bus. Tradeoffs to be looked at when using the JTAG/IEEE-1149.1 standard for ASIC are evaluated. >

Application Research of JTAG Standard Based on ARM Debugging System

Abstract: Currently, the JTAG debugging is the most popular technology in the embedded ARM system. After providing a perfect JTAG debug method based on the GPIO pins of ARM chip, the paper analyzed the inner technology by which JTAG standard was accomplished. At last, the focus has been put on the analyses of the Boundary-Scan Chain working processes.