Showing papers on "State (computer science) published in 1973"

Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic

Abstract: With the increasing complexity of logic that can be fabricated on a single large-scale integrated (LSI) circuit chip, there is a growing problem of checking the logical behavior of the chips at manufacture. The problem is particularly acute for sequential circuits, where there are difficulties in setting and checking the state of the system.

Parallel Counters

Abstract: Multiple-input circuits that count the number of their inputs that are in a given state (normally logic ONE) are called parallel counters. In this paper three separate types of counters are described, analyzed, and compared. The first counter consists of a network of full adders. The second counter uses a combination of full adders and fast adders (that may be realized with READ-ONLY memories), while the third type of counter uses quasi-digital (i.e., analog current summing) techniques to generate an analog signal proportional to the count which is then digitized.

Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops

Abstract: A synthesis method for multiple-input change asynchronous sequential machines is proposed. The method is based on the self-synchronization principle. The internal states are realized with edge-sensitive flip-flops which are triggered selectively. The new concept of selective triggering or controlled excitation results in considerable saving in logic and more flexible design. The state assignment is arbitrary, and the number of state variables required can be made absolutely minimum. A detailed comparison of the speed of operation is made with one of the well-known methods of realization. It is found that our realization is, in general, as fast, and sometimes could be even faster.

Sequential control circuit having improved fault detection and diagnostic capabilities

Abstract: This invention relates to the architecture, fault detection and diagnostic capabilities of a sequential control circuit, or sequencer. The sequential control circuit can be instructed to test any of a number of circuits by executing one of several fixed sequences. The advance from one state to the next in the sequence is dependent on a combination of external signals from the circuit under test, the present sequence state, and the test mode. The new sequence state, in combination with the test mode, cause various actions to take place to further exercise the unit under test.

Digital Computation of SCR Chopper Circuits

Abstract: The formulation of generalized state equations by using binary logic variables decided by the SCR and diode logic modules is discussed. Advantage of this method is that the state equations can be set up without the exact knowledge of the circuit operation. The different modes of operation of the circuit are identified by the computer itself. This method is applied to a chopper circuit with an RL load and the computed results are presented.

System for operating a boiling water reactor steam turbine plant with a combined digital computer and analog control

Abstract: A combined digital computer/analog control system for operating a boiling water reactor steam turbine power plant, wherein the digital computer provides a throttle pressure setpoint, speed error and load demand for controlling the plant depending upon the operational states of the system, is disclosed. The analog portion of the system also controls the plant in cooperation with the digital computer for certain operational states and conditions when the digital computer is in operation; and the analog system alone controls the plant when the digital computer is out of service. The transfer between such control is effected depending upon the operational states of the system and certain of the components therein. The system also includes in the digital computer portion, the provision for preventing a load demand which is outside the limits of the reactor circulation system when the reactor is in a state of automatic operation.

Signal duration sensing circuit

Abstract: A circuit for producing output levels having a first or a second binary significance in response to input signals having a first or a second value, respectively, for a period greater than T. The circuit includes means for sampling and storing the input signal in response to a sampling pulse followed in a time T by a shift pulse. The circuit also includes means feeding back the output of the circuit to its input for preventing any input signal whose duration is less than T from altering the state of the output. The circuit also includes means for overriding the sampling, shifting and feedback controls for passing all input signals to the output of the circuit with very little delay.

Geometric Programming: A Technical State-of-the-Art Survey

Abstract: This paper presents a detailed survey of the latest techniques for solving large geometric programs. Geometric programming is a very powerful method for solving a large class of nonlinear programming problems, but it has been severely restricted in practice due to the inability to handle even moderate sized problems; that is, those possessing more than a few degrees of difficulty. During the past two years, a number of significant break-throughs have taken place in regard to handling both large problems and the general signomial, or signed programs. Several new algorithms, some untested in practice, are presented and discussed in this paper.

Periodic Realization of Synchronous Sequential Machines

Abstract: A new realization scheme is proposed for implementing sequential machines with nontrivial periods. The scheme is primarily based on state assignments related to cyclic partitions on internal states of a sequential machine. Operational linkages of cyclic partitions to the input-independent autonomous clocks of sequential machines are established. Special logic design and IC implementation advantages of the scheme are demonstrated in terms of input and/or state dependencies, logic complexities, and memory requirements of sequential machines.

Electronic circuit arrangement

Abstract: The product of dissipation and delay time is often substantially constant in logic circuits. In the active state, a logic circuit has a higher switching speed and dissipation than in the non-active state. The clock receives the same power supply so that the clock pulse frequency can be automatically adapted to the speed of the other components. Notably when use is made of integrated injection logic in portable apparatus, a saving can be achieved as regards consumption of battery energy, while the circuit itself is hardly more complex.

Restricted Checking Sequences for Sequential Machines

Abstract: This paper shows that the imposition of some restrictions on the realization of a sequential machine facilitates the derivation of efficient checking sequences for some machines. Specifically, it is assumed that the state logic or the output logic may be faulty, but both of them cannot be faulty at the same time. This condition is satisfied if there is no shared logic between the state and output logic and at most a single fault in the circuit. It is also assumed that the normal machine has a synchronizing sequence. With these restrictions on the realization, the machine identification approach may be used to derive checking sequences that are often shorter than those without the restrictions and detect a larger set of faults than with the circuit testing approach.

Device for the automatic adjustment of the amplitude of signals

Abstract: Automatic adjustment of amplitude is carried out on any predetermined half-wave of a recurrent analog signal by means of a device comprising a variable-gain amplifier, a storage circuit for indicating the amplitude of each output signal of the amplifier, a decision logic circuit which assumes a logical state A if the indicated amplitude does not attain a lower threshold level or a logical state D if the indicated amplitude exceeds an upper threshold level, a bidirectional register and a synchronization and control logic system in which means placed at the output of the amplifier eliminate signals smaller in amplitude than a predetermined value and transmit signals to a counter, the state of which is compared with two series of pre-indicated numbers by means of a comparator having outputs connected to the storage circuit and the decision logic circuit.

State of readiness

Abstract: The anniversary of Hurricane Katrina should remind scientists to keep disaster recovery plans in order.

State and sequence detector

Abstract: A system is disclosed which permits the sequence of ocurrence of a plurality of events to be monitored and which prevents operation of a machine unless the monitored events occur in a predetermined order. The system of the present invention is particularly suitable for use with any machine or apparatus which operates in a series of discrete or sequential steps, and which is controlled manually in part and automatically in part. The relative state and sequence detector system of the present invention includes a J-K flip-flop circuit for monitoring changes in the operating state of the apparatus, and further includes a logic network for sensing the condition of a plurality of indicators representing the operating states of a plurality of components within the apparatus. The output of the logic network are used to arm the J-K flip-flop and to supply command signals to the automatic control portion of the machine or apparatus.

M-ary linear feedback shift register with binary logic

Abstract: A family of m-ary linear feedback shift registers with binary logic is disclosed. Each m-ary linear feedback shift register with binary logic generates a binary representation of a nonbinary recurring sequence, producable with a m-ary linear feedback shift register without binary logic in which m is greater than 2. The state table of a m-ary linear feedback shift register without binary logic, utilizing sum modulo m feedback, is first tabulated for a given initial state. The entries in the state table are coded in binary and the binary entries are used to set the initial states of the stages of a plurality of binary shift registers. A single feedback logic unit is employed which provides a separate feedback binary digit to each binary register as a function of the states of corresponding stages of the binary registers. The stages of the binary registers which are fed back depend upon the stages which are fed back through nonzero multipliers in the m-ary linear feedback shift register, utilizing sum modulo-m feedback.

Electrical considerations in the computer aided design of logic circuit interconnections

Abstract: In the past, the physical interconnection problem for digital computer circuits has been solved mostly without considering the electrical properties of the wires or, equivalently, the transfer function of the interconnections. Further, the semiconductor devices, which represent another part of the system, are designed using network analysis computer programs with only secondary considerations given to the interconnections. The purpose of this paper is to establish general relations between the physical and electrical aspects of the interconnection wiring design and to present an overview of the state of the art of interconnection analysis techniques.

Apparatus for controlling functionally severable parts of a computer system

Abstract: Disclosed is apparatus in a computer for selecting the usage of functionally severable parts of the computer, for example, the amount of memory used by a computer having a plurality of memory partitions and an operating program such as the IBM OS/360 supervisor program for determining the allocation and activation of memory space. In the example given the apparatus includes an added register having a plurality of latches linking the ALU output bus to control by enabling or disabling selectively one or more memory partitions in accordance with usage dictated by the operating system program since the register contents are changeable only when the system is in the supervisor state. A meter is coupled to the memories to indicate elapsed time of use of the memory partitions so as to permit charging of a customer based upon usage. The purpose of this abstract is to enable the public and the Patent Office to determine rapidly the subject matter of the technical disclosure of the application. This abstract is neither intended to define the invention of the application nor is it intended to be limiting as to the scope thereof.

Memory write circuit

Abstract: A MOS write circuit includes circuits which are operative during a first interval of a memory cycle of a storage unit to store a predetermined signal to represent a result. During another interval, the circuits logically combine binary information signals applied thereto by the storage unit and a utilization device. In accordance with the result of logically combining the information signals, the circuit selectively modifies the state of a signal representation of the result stored during the first interval. The write circuit further includes output circuits which are rendered operative conditionally by external command signals from the device to switch state during another interval of the same memory cycle in accordance with the stored result as modified, producing complementary output signals representative of either binary ONE or binary ZERO information.

N-state logic circuit

Abstract: An improved electronic circuit having three or more operative stages and suitable for use as a logic element having more than two stable operating states. Each stage of the circuit has a circuit portion which is capable of being rendered operative or conductive while the other stages of the circuit are inoperative or non-conductive. Each stage includes a switch which opens and closes and has a particular output voltage representative of the particular operating state. The output voltages of the three stages are different from each other so that the operating states are discernible from each other. Several embodiments of the basic circuit are disclosed. A counter using a pair of logic elements of this invention is also disclosed.

Digital control processor

Abstract: A digital control processor for controlling a number of relay sets from digital information received from a digital PABX. The digital control processor consists essentially of a first-in first-out memory and a combinational logic unit. The memory stores information relevant to an operation to be performed by the processor and re-cycles the information until the operation has been performed. The memory determines the action of the combinational logic unit which action includes changing the state of one of the relay sets. The action of the combinational logic unit is determined by time varying data states from the memory and/or from a relay set or sets. The digital control processor acts as an interface device between the digital/electronic world of the PABX and the analogue/mechanical world of the public exchange. The device receives digital information from a processor in the PABX and also monitors the current state of all the relay sets. The device accepts a digital signal from the PABX processor in a short time, which information relates to an action to be performed by one of the relay sets and may include information indicating a digit to be transmitted to line in the form of impulses. The device then causes the relevant relay set to perform the desired action without further reference to the PABX processor. The device is capable of locating the relay set which has been in a particular state for the longest period of time upon request from the PABX processor for a relay set in that state.

Tan-Like State Assignments ror Synchronous Sequential Machines

Abstract: Recently, Tan developed a heuristic state assignment algorithm for asynchronous sequential machines. In this paper a state assignment algorithm based on Tan's is developed for synchronous sequential machines. It shares with Tan's algorithm the advantages of simplicity of execution and economy of logic elements in the resulting realizations.

Multiple-input change asynchronous machines using controlled excitation and flip-flops

Abstract: A synthesis method for multiple-input change asynchronous sequential machines is proposed The method is based on the self-synchronization principle The internal states are realized with edge-sensitive flip-flops which are triggered selectively The new concept of selective triggering or controlled excitation results in considerable saving in logic and more flexible design The state assignment is arbitrary, and the number of state variables required can be made absolutely minimum

Sequential-circuit characterisation and synthesis using a 'transition-equation' approach

Abstract: The characteristics of combinational and sequential circuits or networks can be expressed in ‘transition-equation’ form. Transition characteristic equations carry complete information on the behaviour of the circuit, and are readily derived for any circuit or from any reasonable circuit data sheet. Synchronous, clock and asynchronous inputs can be shown, and also the nature of the clock activation, where appropriate. Propagation delays may also be manipulated with the characteristic expressions. Network characteristics can also be expressed in terms of desired transitions from one state to another, and this leads to straightforward synthesis procedures when circuit characteristics are in transition-equation form. Analysis is equally straightforward. The paper briefly introduces transition characteristic equations by way of J-K flip-flops and NAND gates, and then uses a simple example to illustrate the approach to synthesis. It is clearly shown that the transition equations allow for several different approaches to be taken to the same problem. Hazards due to propagation delays are also revealed, which is particularly helpful, for example, when dealing with ‘ripple-through’ arrays.

A new approach to telemetry data processing

Abstract: An approach for a preprocessing system for telemetry data processing was developed. The philosophy of the approach is the development of a preprocessing system to interface with the main processor and relieve it of the burden of stripping information from a telemetry data stream. To accomplish this task, a telemetry preprocessing language was developed. Also, a hardware device for implementing the operation of this language was designed using a cellular logic module concept. In the development of the hardware device and the cellular logic module, a distributed form of control was implemented. This is accomplished by a technique of one-to-one intermodule communications and a set of privileged communication operations. By transferring this control state from module to module, the control function is dispersed through the system. A compiler for translating the preprocessing language statements into an operations table for the hardware device was also developed. Finally, to complete the system design and verify it, a simulator for the collular logic module was written using the APL/360 system.