Showing papers on "State (computer science) published in 1974"

Static state estimation in electric power systems

Abstract: A static state estimator is a collection of digital computer programs which convert telemetered data into a reliable estimate of the transmission network structure and state by accounting for 1) small random metering-communication errors; 2) uncertainties in system parameter values; 3) bad data due to transients and meter-communication failures; and 4) errors in the network structure due to faulty switch-circuit breaker status information. The overall state estimation process consists of four steps: 1) hypothesize mathematical structure; 2) estimate state vector; 3) detect bad data and/or structure errors; and identify bad data and/or structure errors. The problem is characterized by high dimensionality and the need for real-time solutions using limited computer time and storage. Various methods of solution are discussed and compared.

Programmable logic controller

Abstract: A programmable controller includes a processor which executes a control program to alter the state of an output image table stored in a read/write memory in response to the state of an input image table stored in the memory. An input/output scanner circuit connects directly to the read/write memory and periodically steals a memory cycle from the processor to couple the status of input and output devices with corresponding bits in the input and output image tables. The rate at which the scanner circuit operates is independent of the processor speed and is selected to accommodate the input/output interface circuitry on the programmable controller.

Electronic torque wrench

Abstract: An electronic torque wrench including a strain measuring bridge circuit disposed to measure the bending strain of the handle thereof, a NAND gate circuit connected to alternately excite the bridge according to the switching state thereof, a differential circuit connected to receive the bridge balance signal, an integrator connected to integrate a selected polarity output signal from said differential circuit, a clock-driven counter connected to be inhibited for a predetermined time interval following each time the integrating circuit output signal changes polarity providing selected binary level output signals to switch the NAND gate circuit according to the state thereof and a logical switching circuit connected to the selected binary level output signals of said counter for alternatively connecting either the output signal from the differential circuit or a fixed reference signal to the integrator

Analysis of Thermal Deformation of Machine Tool Structure and Its Application

Abstract: A general computer program for the design and analysis of machine tool structures by the use of the finite element method has been completed. The system consists of three parts; the input program for the automatic mesh generation in idealizing the structure, the program for the analysis of the static, dynamic and thermal deformations of the machine tool and an output program to draw the configuration of these deformations and to print out the numerical data requested. A sample computation is carried out on the thermal deformation of a jig grinding machine in the steady and non-steady state as well as in the on—off operation of the machine.

Controller for digital devices

Abstract: Disclosed is a controller which functions to interconnect and control one or more digital devices such as magnetic discs, typewriters and other digital data processing equipment. The controller receives input signals and delivers output signals through interface vector (IV) buffer stores which connect to and from user devices. The logical state of the output signals in the buffer stores is determined by an instruction-controlled processor which accesses instructions from a memory. The instructions are processed in response to input signals (operands) from buffer stores and produce output signals (operands) to the buffer stores. The instruction fetching paths and the operand fetching and storing paths are separate. The controller includes apparatus and an instruction set which allows variable fields in the buffer stores to be addressed to provide source operands and to be addressed to store result operands after instruction execution.

A self-reorganizing digital flight control system for aircraft

Abstract: This paper presents a design method for digital self-reorganizing control systems which is optimally tolerant of failures in aircraft sensors. The functions of this system are accomplished with software instead of the popular and costly technique of hardware duplication. The theoretical development, based on M-ary hypothesis testing, results in a bank of M Kalman filters operating in parallel in the failure detection logic. A moving window of the innovations of each Kalman filter drives the detection logic to decide the failure state of the system. The detection logic also selects the optimal state estimate (for control logic) from the bank of Kalman filters. The design process is applied to the design of a self-reorganizing control system for a current configuration of the space shuttle orbiter at Mach 5 and 120,000 feet. The failure detection capabilities of the system are demonstrated using a real-time simulation of the system with noisy sensors.

Design of Diagnosable Sequential Machines Utilizing Extra Outputs

Abstract: This paper is concerned with the problem of designing easily testable sequential machines, output-observable machines, for which there exist very short checking experiments. A sequential machine for which any initial state can be uniquely determined only by the output response is said to be output-observable. An algorithm is developed to modify a given machine to an output-observable one by adding a minimum number of extra outputs. This method is based on the fact that the output-observable realization of a given machine M exists if and only if M is semi-FSR realizable (a special type of feedback shift register realization).

Digital logical sequence controller

Abstract: A sequence controller of the digital logical circuit type, comprising a sequence program part and a processing circuit, wherein the desired sequence instruction is read from the sequence program part, and the sequence is processed and controlled by the processing circuit. A certain definite level is set at a branch point in an equivalent sequential circuit according to the path along which a signal of the sequential circuit is transmitted. This level and the on-off state of the branch point are stored in a memory. The given data are processed and controlled through the sequence program part and the memory.

The design of cellular arrays for arithmetic

Abstract: The past five years have seen the rapid development of iterative circuits performing many arithmetic functions. With the present state of l.s.i. technology in mind, this paper retraces the basic steps made in iterative circuit design and suggests that pipelined arrays are the most suitable for manufacture. The paper also suggests how general arithmetic arrays can be modified to perform non-arithmetical functions.

Apparatus for operation selector circuits, especially tariff selector circuits in electronically operated taximeters

Abstract: An electronic taximeter having a fare computing unit, a selector circuit and an operation switching unit. The fare computing unit computes a fare at a rate determined by logic signals developed by the selector circuit, which is responsive to signals applied thereto. The operation switching unit is operable to develop selected operating signals to determine the logic signals developed by the selector circuit. The selector circuit remains in an operating state determined by the last operating signal applied thereto, even after the last operating signal is removed, until a new operating signal is applied to change the logic signal output of the selector circuit.

A critical look at the state of our science

Abstract: Denning has openly raised the question with which many of us have been bothered for some time: \"What is structured programming?\" We use other such terms which are vaguely (or only intuitively) defined, the most flagrant of which would undoubtedly be the infamous \"virtual\" which we indiscriminately apply to just about anything from I/0 device through memory, processor, machine and even machine architecture.

Programmable logic controller with flag storage

Abstract: A programmable logic controller has input elements sampled to determine status in each of multicomponent lines of a relay ladder network. Output elements in the network connect power voltage sources to power utilization units and disconnect the same in accordance with a programmed set of instructions stored in a controller memory to satisfy operating conditions required of the ladder network. Sample means sequentially generate a set of one bit words, one word representing the state of each of the input elements. A set of one bit output control states is generated, one state for each output element in dependence upon the states of the input elements. Timing means operable once each half cycle of the power voltage initiates generation and storage in a semiconductor read/write image register of one bit input words and output control states. Further, the timing means includes control means for sequentially instituting a serial I/O mode in which the input elements are sampled and the output states are read out of the register and applied to the output elements followed by a run mode in which a new set of control states is established and stored in the register.

Universal condition latch in an electronic digital calculator

Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a universal condition latch which is so connected as to permit the state thereof to be determined by multiple sources while reducing the number of ROM instructions required and hence the size of the ROM to permit fabrication on the smaller chip. The condition latch state is determined, for example, by the logical OR of up to four flags after a test flag instruction, by the logical OR of up to four keyboard inputs after a test key instruction, by the carry output of the adder after any add instruction, or by the results of an adder compare after any compare instruction.

Variable threshold digital correlator

Abstract: Herein is disclosed a circuit adapted for determining whether or not the number of corresponding bits in two parallel arrays of binary signals, which are of the same binary state, exceeds a preselected number. In accordance with one embodiment of the invention, a parallel array of cascode logic circuits is employed wherein each cascode circuit provides differential currents which are indicative of whether or not two applied bits, one from each signal array, are of the same binary state. Differential output currents from a programmable current source are summed with the differential currents from the cascode circuits and the resultant sum signal is applied to a comparator circuit whose output signal is indicative of whether the degree of correspondence between the two arrays exceeds a level determined by the programmable current source.

Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory

Abstract: A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state when a fault exists is described. Finally, some extensions of the technique are attempted.

A Fail-Safe Asynchronous Sequential Machine

Abstract: This paper examines the dynamic fault behavior of asynchronous sequential machines, specifically identifying the faults which cause critical races and hazards, and presents a state assignment technique leading to a machine that enters one of a small set of error states whenever a fault occurs. Entry into an error state can be checked by very simple check circuits; a self-testing check circuit and one requiring only two tests for fault detection are discussed. An extension of the state assignment technique to produce a machine that is fail-safe is also presented. The fail-safe design has the property that once a fault has caused the machine to malfunction and enter an error state, the machine never leaves the error state and therefore does not produce erroneous outputs. This machine detects all but a small class of multiple faults.

A State Assignment Technique for Sequential Machines Using J-K Flip-Flops

Abstract: Several techniques for choosing state assignments which tend to minimize the combinational input and output circuitry of sequential machines have been developed One of these techniques is a heuristic scoring approach which was originally developed assuming delays as memory elements [1]

Method and device for recording, in real time, non uniformly variable data with compression of data during periods of relatively slow variation thereof

Abstract: The data is stored in the digital mode. The device comprises a sampler and converter from the analogue to the digital mode, a first set or cascade of shift registers for data, a computing and comparison unit with switching means, a second set or cascade of shift registers for the time intervals, addition units adding one digit (+ 1), subtraction units, a logical unit with control units, and a memory or storing unit. The device may be used in a high voltage station for monitoring an electrical network to detect possible faults. The object of this invention, is to provide a method and a device for recording, in real time, non uniformly varying data with compression of data during periods of relatively slow variation thereof. Already known are data recording methods and devices which store, in digital form, data representing a variable phenomenon, the variation of which is produced at variable frequency, for example when it is a matter of both a permanent process (or operation) and a transient process (or operation). In this case, it is necessary, if it is wished to avoid making use of a very big storage capacity, to proceed with the compression of data during periods when the phenomenon under study varies slowly with respect to time. For example, the "fan" method is known. In this method, the frequency with which the sampled data is stored, follows a very complex law, which makes it difficult to code the instants of sampling, at the same time involving material errors between the compressed signal which is stored, and the original signal which corresponds to the phenomenon under study. It was also suggested to carry out the recording at a slow rate for the permanent process and at a very high rate for the transient process, but problems arose concerning the transfer from one rate to the other and the synchronization between the recording and the phenomenon. The storing of data on a magnetic record in analog form was also used but such a method requires a very wide pass band, and therefore, in the corresponding device, a very high tape speed of the magnetic recording carrier (tape or disk) relatively to the magnetic recorder heads which limits the duration of the phenomenon being stored unless very cumbersome mechanisms and carriers are used. Such a magnetic record also needs high precision rotary devices to be used and generally has to be operated in a controlled environment. The object of this invention is to provide a method and a device which allows an efficient compression, and therefore a smaller storage capacity for the recording of a relatively long phenomenon, with a small error between the reproduced signal from the recording and the original signal produced by the phenomenon under study. The method, according to the invention, for recording, in real time, non uniformly variable data, with the compression of data during periods of relatively slow variation thereof, is characterized by the fact that it comprises in combination, ON THE ONE HAND, THE FOLLOWING SUCCESSIVE OPERATIONS: CONSTANT RATE SAMPLING OF DATA IN DIGITAL FORM; STORING THE SAMPLED DATA IN THE FORM OF A SERIES WITH A DETERMINED NUMBER OF SUCCESSIVE SAMPLED DATA; STUDYING, DURING NORMAL FUNCTIONING OF A SET OF THREE SUCCESSIVE DATA STORED FROM THAT SERIES TO CHECK IF THE DIFFERENCE BETWEEN THE CENTRE DATA OF THIS SET OF THREE AND THE ARITHMETIC MEAN OF THE TWO EXTREME DATA THEREOF IS SUPERIOR OR INFERIOR, IN ABSOLUTE VALUE, TO A GIVEN LIMIT; PERFORMING IN RESPONSE TO SAID CHECKING, OF ONE OR THE OTHER OF THESE TWO OPERATIONS: THE FIRST, WHICH IS CARRIED OUT IF THE AFORESAID DIFFERENCE IS INFERIOR, IN ABSOLUTE VALUE, TO THE SAID LIMIT, CONSISTS IN SUPPRESSING THE CENTRE DATA OF THE SET OF THREE AND TO INCREMENT BY ONE ROW IN THE SERIES ALL THE DATA WHICH COME AFTER THE SUPPRESSED MIDDLE DATA, THE SECOND, WHICH IS CARRIED OUT IF THE DIFFERENCE IS SUPERIOR, IN ABSOLUTE VALUE, TO SAID LIMIT, CONSISTS IN MEMORIZING THE OLDEST DATA OF THE SERIES BY INCREMENTING BY ONE ROW ALL THE STORED DATA OF THE SERIES OF DATA; STORING A SAMPLED DATA IN THE MOST RECENT ROW OF STORAGE WHICH HAS JUST BEEN VACATED BY THE FORWARD MOVEMENT OF PART OR ALL OF THE DATA ALREADY STORED; AND ON THE OTHER HAND, IN PARALLEL WITH THE PRECEDING OPERATIONS OF STORING, STUDYING FORWARD MOVEMENT AND MEMORIZING OF SUCCESSIVE DATA, THE SUCCESSIVE OPERATIONS OF STORING AND MEMORIZING THE TIME INTERVALS SEPARATING THE EFFECTIVELY STORED, AND THEN MOMORIZED DATA. A device, also according to the invention, for embodying said method comprises, in combination: a constant rate sampler for data in digital form; a first cascade set of shift registers, the input of the first register of this stage being connected to the output of the sampler, for the storing of sampled data; a calculator and comparator unit, with three data inputs, designed to differentiate between the signal on its second input and the arithmetic mean of the signals on the first and third inputs and to compare the absolute value of this difference with a limit value applied in the form of a signal on a fourth input; switching means, the inputs of which are connected to the outputs of the shift registers of the first set and which is designed to switch to their three outputs, which are connected to the three inputs of the comparator unit, three consecutive outputs chosen from among the outputs of the aforesaid registers; a second cascade set of shift registers, the number of which is equal to the number of registers of the first set less one unit, for recording the time intervals between data stored in the registers of the first set; adder units to add one unit to the signal applied on its input, connected between the successive registers of the second set of registers as well as being upstream the first register of this set; subtracter units to subtract the value of the input of the adder unit preceding it from the value of the output of the registers of the second state; a logic unit, the inputs of which are connected to the outputs of the aforesaid subtractor units and which determines the three successive registers of the first stage the outputs of which will be connected through said switching means to the calculator and comparator unit; a control unit transmitting the decisions of the logic unit to the switching means to the registers of the first and second sets and to the adder units; and a storing or memory unit with one part, the input of which is connected to the output of the last register of the first set, and a second part, the input of which is connected to the output of the last register of the second set.

Electronic calculator implemented in semiconductor LSI chips with scanned keyboard and display

Abstract: An electronic desk top calculator implemented in MOS/LSI technology and including a scanned keyboard input and display output. Data registers are provided in a sequentially addressed random access memory array, which is addressed by a commutator also used to generate encoded timing signals for other parts of the system and control logic. The keyboard input includes an interface register into which is entered key sense line information along with encoded timing information derived from the encoded timing signals. The contents of the interface register may be entered into the data registers or used to select an address in a program storage memory via a program counter. Bits may be read out in parallel from cells in the data registers and processed through an arithmetic logic unit and then re-entered in the same cells within a bit time or state time, so the data registers do not recirculate in the usual sense.

Simplification of some time-optimal switching functions

Abstract: The time-optimal switching functions for certain plants can involve fractional powers of functions of the state coordinates. A technique is given for obtaining equivalent switching functions which do not contain fractional powers, and are thus simpler to generate, especially in digital simulation studies.

Digital computer simulation of inductor-energy-storage dc-to-dc converters with closed-loop regulators

Abstract: The simulation of converter-controller combinations by means of a flexible digital computer program which produces output to a graphic display is discussed. The procedure is an alternative to mathematical analysis of converter systems. The types of computer programming involved in the simulation are described. Schematic diagrams, state equations, and output equations are displayed for four basic forms of inductor-energy-storage dc to dc converters. Mathematical models are developed to show the relationship of the parameters.

State notation and SKED: A general system for control and recording of behavioral experiments

Abstract: State notation is a language for describing behavioral procedures and data acquisition formats. A minicomputer system has been developed for translating state notation into operating computer programs, which can control 10 simultaneous and independent experiments. A description of the system is provided, including the hardware necessary to interface the computer with the experimental environment

Notion of dynamical input-output systems: causality and state concepts

Abstract: A basic mathematical formalism of dynamical systems is presented from the view-point of control engineering. The notion of input-output systems is given in a general logistic format in which most of the detailed system models can be embedded. Concepts of time, time system, causality, and state are introduced. The time system is of a generalized form in which the time domains of component functions of input and output may be different from each other. The causality is a term for the traditional non-anticipation. The state is introduced firstly in a pure form. Then a state representation, state mapping, state transition, and a static output system are formalized. The results of discussion and propositions show close interrelations between the causality, state mapping, and static output system.

A computer algorithm for the optimization of discrete-time pulse frequency modulated systems

Abstract: A computer algorithm is described for the optimization of discrete-time pulse frequency modulated systems with state and control constraints. The algorithm, based on a modified maximum principle [1], leads to the solution of a Boolean linear programming problem, for which many computer codes are available commercially. An application to a time-shared sampled-data control system is presented. Numerical examples are given.

The design of sequential logic circuits

Abstract: The inadequacies of Combinational and Sequential Logic as circuit design techniques are pointed out; in particular, the Sequential Logic design technique due to Huffman has the disadvantage of leading to 'race' problems. The work of Moore on Finite Machine Theory points the way to design based on a state graph and this technique is advocated. An illustrative example of this technique is adduced. The case is made for the direct implementation of the state graph as a good design method and a novel logic element is proposed which is an analogue of a node on a state graph.

Asynchronous sequential machines with request/acknowledge operating mode

Abstract: A method for the synthesis of asynchronous sequential machines that leads to a realisation directly obtained from the flow graph (or flow table) is described. Each state of the system is materialised with a memory element designed in such a way that the state transitions operate in a request/acknowledge mode. The consequences are that the sequential network is hazard free and only the input transfer functions need to be generated.

Control system having a programmed logic unit

Abstract: Programmed logic control system intended for the monitoring of a set of elements, more particularly a switching exchange comprising an addressable memory containing the list of orders enabling the said monitoring, input detectors receiving the data concerning the state of the various controlled elements, registers for storing the data used by the program, output means enabling the sending, towards the elements, of orders for the changing of state and/or digital data contained in the registers and means for addressing the memory effecting an analysis according to a logic unit comprising several states of the input data.

Picture systems, PS, and the design of a channel-to-channel computer interface

Abstract: This paper introduces a new simulation tool called picture systems. A picture system is (1) a set of pictures - one representing each state of a modeled computer system and (2) a transition graph which relates each picture to the set of pictures that may follow it. Picture systems can be used to model computer systems at any level of detail; however, this paper is concerned with modeling hardware/software systems at relatively high architectural levels. Picture systems, as a simulation tool, are useful to the computer architect. Perhaps more importantly, they provide an unexcelled means of communicating computer system mechanisms between people.The construction of picture systems from descriptions of the components of a computer system has been automated in PS. This paper describes a model of a channel-to-channel computer interface mechanism consisting of both hardware and software. Transition graph analysis by PS is briefly described. This powerful aid to computer system modeling eases the identification of problems such as deadlock, looping, and races.