Showing papers on "State (computer science) published in 1975"

Microprogram controlled digital processor having addressable flip/flop section

Abstract: A digital processor which is adapted for use in the guidance and stabilization of a guided missile. The digital processor is adapted to store a predetermined macroprogram and to process signals produced by various elements within the missile in accordance with such stored program thereby to produce control signals for the missile's flight control mechanism. A microinstruction memory stores sets of microinstructions, each one of such sets corresponding to one of a number of stored macroinstructions which make up the macroprogram. A register is provided which is adapted selectively to load an addressed microinstruction or a digital test word serially applied by sources external to the missile. In such an arrangement the missile's digital processor may be readily checked out through a relatively simple interface mechanism, also included. In the digital processor is a set of addressable flip/flops adapted to be set or reset by signals both internal to and external to the processor. The state of an addressed one of the set of flip/flops serves as a condition signal used in the execution of various ones of the microinstructions. The output of the macroprogram storage memory is adapted to be coupled to the address inputs of the data memory thereby enabling retrieval of both an instruction from the macroprogram memory and its corresponding operand from the data memory within a single clock pulse interval.

High speed divide-by-N circuit

Abstract: Disclosed is a high speed divide-by-N circuit which uses both a synchronous down-counter and a ripple down-counter to obtain the advantages of each. The advantage of a ripple counter is that count propagation time is not critical, and the advantage of a synchronous counter is that its state can be decoded quickly. Therefore, by combining the two different types of counters, keeping the gate delays per clock cycle as low as possible, using look-ahead techniques, and giving more time-consuming operations more time to occur, a high speed divide-by-N circuit is obtained. Said circuit is intended for integration on a single chip, particularly using CMOS design and processing.

Design of Asynchronous Sequential Networks Using Read-Only Memories

Abstract: The application of microprogrammed READ-ONLY memories in the design of asynchronous sequential networks is investigated. Variations of single-transition time (STT) state assignments are shown to be applicable to the problem of assigning memory addresses to a memory representation of an asynchronous network. Design algorithms are developed which allow the implementation of an asynchronous sequential network as a READ-ONLY memory. Two operating modes are considered: normal asynchronous operation and a self-clocked mode in which sequential outputs are allowed on a single-input change, thus providing a means of implementing functions normally achieved with synchronous (clocked) networks. In addition the practical timing constraints of the proposed methods are considered.

Flip-flop false output rejection circuit

Abstract: An asynchronously timed digital flip-flop circuit eliminates malfunction occurring when internal race conditions cause the flip-flop to lock up at the guasi-stable threshold state in which both input and output signals of the flip-flop are not at true logic levels but are equal to each other. The addition of special circuitry to reject these "false" outputs eliminates their propagation in the digital system in which said flip-flop is employed.

Minimal dimension inverses of linear sequential circuits

Abstract: The concept of an elementary null sequence of a linear sequential circuit is introduced. Its properties are used to formulate a necessary and sufficient condition for the invertibility of a linear sequential circuit and to determine the minimal dimension of an L -delay inverse. A general method is given for constructing a minimal dimension inverse which utilizes the state description of the original linear sequential circuit and which applies whenever L = 0 or whenever the next-state map of the linear sequential circuit (LSC) is onto.

Arrangement for monitoring the state of memory segments

Abstract: In a system for monitoring groups of memory locations in the working memory of a computer equipped with a central processing unit, each location having a capacity of n binary bits, in order to effect automatic location of a group of successive empty locations, which group has a length L at least equal to that required by an interrogating program, and to return a group of memory locations whose contents are no longer required to an unoccupied state and combine such group with following unoccupied groups, there are provided: a memory state register and a base address status register each having a plurality of stages, with each stage corresponding to a respective working memory location and being in one binary state when its corresponding memory location is occupied and in the opposite binary state when its corresponding memory location is empty; an arithmeticlogic function unit including an adder circuit and an indicator circuit connected to the registers for locating a group of successive empty working memory locations by determining the binary states of blocks of adjacent stages of each of the registers; a first group of status flip-flops divided into two blocks, a first one of the blocks being connected to be interrogated by the central processing unit; and a control mechanism connected to the registers, the function unit and the status flip-flops and arranged to interrogate the second one of the blocks of flip-flops, the mechanism being arranged to selectively process the contents of the registers according to one of a selected plurality of modes or to go through a waiting loop in dependence of the states of the flip-flops, and to emit control signals determining the mode according to which the contents of the registers are to be processed.

Triple state to binary converter

Abstract: A logic circuit for converting a triple state input to a binary output having a single line ternary input and a two line binary output. A pair of output transistors provide the two line binary output, and means are provided for driving both of these output transistors, such that three different binary output states result from the ternary input states of low, high and open (or floating), respectively.

Self-checking read and write circuit

Abstract: A self-checking read and write circuit interfaces a control circuit with a plurality of peripheral circuits. The read and write circuit receives address and data commands from the control circuit, decodes the commands and produces a driving signal to operate relays in the peripheral circuits. The read and write circuit also receives inputs from the peripheral circuits indicating the state thereof, multiplexes and inputs and forwards them to the control circuit under control of address signals. The circuit is self-checking in that a readout multiplexor which scans for state changes in the peripheral circuits has its even parity inputs connected at the outputs of the drive signal decoder and its odd parity inputs connected to the scanned points. A parity check circuit on the multiplexor address leads determines whether the address has even or odd parity. If the parity is even, the output of the multiplexor is compared to the output of the drive signal decoder. If the parity on the address leads is odd, the output of the multiplexor is forwarded to the processor. A single hardware failure in the multiplexor address circuitry causes a failure in one of several modes involving a shift in parity values. These failure modes are detected when the output of the multiplexor is compared to the output of the drive signal decoder.

Expandable function electronic calculator

Abstract: An electronic portable calculator implemented in MOS/LSI technology and including a scanned keyboard input and display output. The calculator system utilizes a plurality of output terinals on the primary MOS/LSI chip for selectively addressing in timed coded sequence an array of peripheral MOS/LSI chips providing for expanded register and memory capacity and for output printing. Data registers are provided in a sequentially addressed random access memory array, which is addressed by a commutator also used to generate encoded timing signals for other parts of the system and control logic. The keyboard input includes an interface register into which is entered key sense line information along with encoded timing information derived from the encoded timing signals. The contents of the interface register may be entered into the data registers or used to select an address in a program storage memory via a program counter. Bits may be read out in parallel from cells in the data registers and processed through an arithmetic logic unit and then re-entered in the same cells within a bit time or state time, so the data registers do not recirculate in the usual sense.

Modulus counter circuit utilizing serial access

Abstract: A circuit provides the dual functional capability of a modulus counter and a shift register, and does not require parallel access of the storage elements to preset or read the counter state.

Test device for simultaneously displaying the level of logic signals in a plurality of circuits

Abstract: A test clip suitable for connection to a plurality of terminals at which appear respective logic signals representing those occurring in logic circuits provides an indication of the logic level of such signals. The circuit for effecting such indication is entirely self-contained requiring no external power source or grounding connection and includes a plurality of respective input lines connectable to such terminals with a respective indicator shunted by a reverse poled diode connected to each input line and one common connection for all the diodes and indicators. Thus, for example, a logic 1 signal occurring on one of the input lines will effect a current flow through a respective indicator to change the state thereof with a return current flow path being provided from the common connection through at least one of the shunting diodes connected to another input line then at logic 0 relatively ground potential. The circuit may be easily extended to test simultaneously as many circuits as desired, and such test circuit is effective to operate on positive logic as shown as well as on negative logic, the latter being achieved simply by reversal of the shunting diodes.

Ic use measuring device

Abstract: PURPOSE: To make the effective measurement of the electric characteristions of IC in state of temperature-ris possible. COPYRIGHT: (C)1977,JPO&Japio

Multiple application control system for memory device

Abstract: PURPOSE: To avoid simultaneous multiple application of a memory area by transmitting information held by an application state indicator and an applied computer identifier to another computer. COPYRIGHT: (C)1976,JPO&Japio

Digital program for solving the linear stochastic optimal control and estimation problem

Abstract: A computer program is described which solves the linear stochastic optimal control and estimation (LSOCE) problem by using a time-domain formulation. The LSOCE problem is defined as that of designing controls for a linear time-invariant system which is disturbed by white noise in such a way as to minimize a performance index which is quadratic in state and control variables. The LSOCE problem and solution are outlined; brief descriptions are given of the solution algorithms, and complete descriptions of each subroutine, including usage information and digital listings, are provided. A test case is included, as well as information on the IBM 7090-7094 DCS time and storage requirements.

Superconductive sensing circuit for providing improved signal-to-noise

Abstract: A superconductive sensing circuit having improved signal-to-noise ratio is provided for use with logic circuits using logic switching devices The sensing circuit includes a first and second branch in parallel wherein the first branch includes a Josephson switching device The first branch also includes a first inductance and the second branch includes an inductance greater than or equal to the first inductance The Josephson device in the first branch of the sensing circuit is biased to switch into it's finite voltage state so that the gate current from the logic circuit is directed to the second sensing branch The Josephson device in the first branch automatically resets to it's no voltage state so that subsequent input current is divided between the two branches inversely proportional to the inductances therein This subsequent current in the first branch of the sensing circuit is sensed and is indicative of the switching of one or more of the logic devices in the logic circuit

Design of Reliable Synchronous Sequential Circuits

Abstract: Fail-safe synchronous sequential machines produce safeside outputs when failures occur within the machine. This correspondence presents a procedure to design such machines using a modification of the on-set equation form originally presented by Tohma et al. [1] and later improved by Diaz et al. [2]. A systematic procedure for state assignment and next-state equation derivation, using partition theory, is presented. From this method an easily calculated upper bound on the number of gates required-to realize a fail-safe circuit is derived.

A new OS/8 SKED

Abstract: A new SKED run-time system and compiler have been designed for use under the OS8 operating system. OS8 is a set of programs designed by DEC for the PDP8 computer with 8K or more core memory locations and a mass-storage device (disk, or DEC-tape). The advantages of OS8 include operator convenience, device independent input-output, standard file formats, and convenient program chaining as well as a set of standard data analysis programs. The new compiler, OSCOMP, differs from the previous version in two ways. The first new feature is the ability to process named input and output files on any OS8 compatible peripheral. The second feature is the utilization of 8K of core, permitting compilation of longer state tables than could be processed with the earlier version. Furthermore, with a disk as the OS8 peripheral, the compilation process is essentially instantaneous, for state tables previously requiring from 3–30 min with paper tape devices. The new run-time system, OSRTS8, contains a variety of new features. The most important improvements are the abilities to record data on the OS8 peripheral as well as to read state tables stored as files on the mass-storage device. Other new features include chaining of state tables, automatic start, automatic output file specification, and capability for as many as 12 simultaneous stations.

Methods for teaching program verification

Abstract: “Program verification” is generally defined as the process of ascertaining and demonstrating that a program is correct, i.e., that a program satisfies a given set of specifications. The most common method of verifying a program is by testing, the process of executing a program for a set of selected inputs and inferring from the results of those executions that the program is correct for all possible inputs.In practice today, a few programs are being proved correct but the most common method of program verification is still testing. Both methods are unreliable in different ways, but when combined, their complementary relationship can provide a high degree of assurance that programs are correct. The purpose of this paper is (1) to review the state of the art of these two approaches to program verification and the relationship between them, and (2) to suggest a number of ways in which program verification can be introduced into the computer science curriculum.

Programmed Control of Asynchronous Program Interrupts

Abstract: Publisher Summary Few high-level programming languages have sufficient richness to give the user the explicit ability to control asynchronous and independent parallel processes. This chapter discusses the problems associated with the handling of externally caused asynchronous interrupt conditions and presents extensions to existing languages that provide a capacity for interrupt handling. The primary goal of this article is to define and illustrate an attention-handling facility embedded in a high-level programming language. The PL/I programming language is used as a basis for many examples because it already has a rudimentary capacity in this area. However, consideration is given to other common languages such as FORTRAN and COBOL. Two basic control structures are used in the development: “on-units” and a facility achieved through the synchronization of independent tasks. The primary area of concern is what happens to a running program as the result of an event or condition arising “outside” of the main program stream such as might result from an I/0 (Input/Output)device, graphical terminal, or online process controller. Upon encountering this situation, a special segment of code is executed. This article begins with a tutorial overview and a brief survey of the current state of the art, followed by a suggestion of a possible extension to existing facilities.

Fail-Safe Asynchronous Sequential Machines

Abstract: Fail-safe circuits are designed to assume a 1 (1-fail-safe) or a 0 (0-fail-safe) output state upon failure. This correspondence extends fault detection techniques previously presented [1] to include the design of fail-safe asynchronous sequential circuits. Faults causing failures in the internal state logic and the output state logic circuitry are treated. These failures are assumed to be symmetric and the resulting circuit realizations require less hardware than realizations derived from previously presented techniques.

Control and correction circuit for an electronic watch

Abstract: A control and correction circuit for an electronic watch involving three push-buttons which are actuable to select and/or correct the information displayed by the watch The push-buttons provide actuating signals to a delay device and to logic selection circuits which provide outputs to control the counters of the watch circuit The delay device enables a secondary display to be displayed for a predetermined time after which the device returns to its initial state During the predetermined time the information displayed may be corrected by actuation of the second or third push-button in which case the secondary display is held unitl the correction operation is complete before returning to its initial condition

General purpose digital logic monitor

Abstract: For servicing digital logic circuits, a hand-held monitor can be connected to an indefinite number of different sets of test points. Numerical and binary displays indicate the current state of the selected test points. To help the user understand what is being monitored, removable cards can be mounted adjacent the displays. Each of the cards has printed information relating to a different set of test points. An operator-controlled auxiliary clock is included to permit the operator to step the circuit being monitored through its operating sequence.

Delayed Universal Logic Modules and Sequential Machine Synthesis

Abstract: A universal logic module of n variables (ULM-n) can be considered as a 2n-in-1 multiplexer (inverse binary tree) whose code is determined by the presentation of external variables. This interpretation permits synthesis of sequential machines. Starting from the state transition map, any sequential machine can be realized by delayed ULM's and OR gates. The decomposition concept of Weiner and Hopcroft is generalized to form a uniform synthesis of n-variable sequential machines.

Information control device

Abstract: PURPOSE:To enable the control of FIFO by connecting an FF circuit with a signal input line and with a signal take-out line and arranging an inverter in the output of an NOR circuit constituting the FF circuit to indicate the stored or empty state of information.

Operation state monitoring apparatus

Abstract: An operation state monitoring apparatus for monitoring an operation state of a controlled object is disclosed. The apparatus compares actual operation state data of the controlled object with reference operation state data of the controlled object read out from a reference operation state data memory and sets desirable data selected from the actual operation state data to the reference operation state data memory as the reference operation state data.

Driver for logic switching cct. - sender and receiver gates are connected to data collecting line

Abstract: A logic input circuit distributes binary signals applied to its signal input, to the two outputs in accordance with a control signal applied to its control input A level converting stage retransmits these signals or stops them in accordance with a reference voltage and the logic input circuit output signals A push-pull output stage consisting of a pair of complementary transistors connected by their collectors and controlling the logic switching circuits delivers the binary signals when the driver circuit is in its active state Its internal resistance is high in the passive state