Showing papers on "State (computer science) published in 1977"

The Indirect Binary n-Cube Microprocessor Array

Abstract: This paper explores the possibility of using a large-scale array of microprocessors as a computational facility for the execution of massive numerical computations with a high degree of parallelism. By microprocessor we mean a processor realized on one or a few semiconductor chips that include arithmetic and logical facilities and some memory. The current state of LSI technology makes this approach a feasible and attractive candidate for use in a macrocomputer facility.

Digital computer monitoring and restart circuit

Abstract: Case 04-4071-U.S. APPLICATION OF JAMES A. HOGAN AND MORTON SKLAROFF DIGITAL COMPUTER MONITORING AND RESTART CIRCUIT ABSTRACT A digital computer monitoring and restart circuit monitors the presence of periodic output signals from the digital computer by a missing pulse detector. When the detector senses a missing output signal from the computer, it indicates this detection operation by an output signal representation of the fact that the computer is not operat-ing. In response to this output signal a restart pulse is generated by a restart pulse generator and is applied to the computer to restart the computer and to reset the monitoring circuit Concurrently, a five-second timer circuit is started. While the timer circuit is operating over its five-second interval, if the monitoring circuit produces another output signal indicating that the computer is not operating, the five-second timer is stopped and an-other restart operation is not attempted. If the five-second timer is allowed to run to the end of the five-second interval without the detection of a computer outage, the monitoring and restart circuit is reset by the five-second timer to an initial state indicative of the continu-ing operation of the computer while awaiting a subsequent computer outage.

Programmable simulated trainer

Abstract: A computer based trainer employing a microprocessor connected to a program memory and input and output devices by means of common address and data buses. The input devices include a plurality of student operable switches, associated with a pictorial presentation of the lesson subject, which are interconnected in a switch matrix whereby the state of the individual switches may be sensed by energizing columns and sensing rows of the matrix under control of a stored program. The teaching machine also utilizes a non-volatile memory in which at least a portion of the program is stored.

An Automatic Optical Printed Circuit Inspection System

Abstract: With the trend toward higher circuit density and finer lines, printed circuit inspec-tion becomes more important both in terms of assuring adequate functional capability, aswell as long term reliability. Visual inspection of such circuits in a high volume produc-tion environment becomes more difficult, prone to error, and expensive. Automatic opticalinspection appears to provide the only effective means of performing this operation. Sucha method has application not only for final product inspection, but also for inspection atintermediate stages of production including art work inspection.A practical system must be able to convert the printed circuit pattern into a binarytwo -dimensional representation and then to process this representation to detect flaws.Development of the binary representation is hindered by the low optical contrast presentedby many printed circuit material systems. The detection of flaws depends on selecting errorcriteria that are indicative of circuit quality, and that are practical to implement.This paper describes a prototype automatic inspection system which uses minimum linewidth and line clearance criteria. This system provides high resolution and uses linearsolid state arrays for sensors. The conversion to a binary representation is made aftercorrecting for system spatial nonuniformities in the illumination, optics, and sensingelements. Internal registers, which are continually being updated, are used to storesuccessive scans of the image. At the same time, the contents of the registers areprocessed in parallel using combinatorial logic to implement the error criteria.IntroductionAs printed circuits become denser with finer lines and closer clearances betweenconductor paths, the task of evaluating circuit quality in the manufacturing processbecomes more important. Such an evaluation is needed to insure adequate functionalcapability, long term reliability, and to maintain control of the manufacturing process.At the same time the task of evaluating the product by means of visual inspectionbecomes more difficult, more subject and prone to error, and more expensive. It hasbeen estimated that as much as 40% of the cost of some printed circu.iG goes for inspectionand testing. It follows that an accurate and economic automated means of assessing circuitquality is needed.One approach to this is the use of more extensive electrical testing. In additionto functional short circuit and continuity testing, high voltage breakdown measurementsmay be used to monitor minimum conductor clearance, while circuit path resistancemeasurements can test for unacceptably narrow conductors. At the present time, however,there is no practical electrical means of detecting nicked conductors. Also, electricaltesting is applicable only to final product inspection; i.e., after the circuit patternhas been formed.Automatic optical inspection has the potential of detecting all forms of printedcircuit defects, including nicked conductors. In addition, it can be applied atintermediate production stages, including inspection of the initial artwork. This latterproperty makes possible the early discovery of manufacturing problems which could resultin considerable savings of material and time.Recent advances in large scale integration digital circuits and solid state multi -element optical sensors make the realization of rugged, inexpensive, compact, automaticinspection systems possible. A prototype of such an inspection system now under develop-ment and evaluation at a Western Electric printed circuit manufacturing plant in Richmond,Virginia is discussed here.The error detecting process may be separated into three steps: data extraction, dataprocessing, and out:uti_o of the result. The first step consists of optically sensing thesample to obtain usable analog or digital signals. Accurate implementation of this step isa prequisite for the succeeding steps. The data thus obtained must then be processed.This involves selecting error criteria that are indicative of circuit quality and that arepractical to implement. Finally, the presence of flaws must be clearly communicated.

Microprogrammable control processor for a minicomputer or the like

Abstract: A minicomputer comprises a microprogrammable central processing unit wherein micro-instruction execution speed is optimized through the use of variable micro-instruction timing logic and by grouping micro-instruction according to execution time. Furthermore, data paths are arranged so that micro-routines that implement more complex operations, i.e., memory reference instructions, follow the fastest route possible. When micro-instructions requiring longer data paths are programmed, the computer dynamically varies the length of the microcycle to be a function of both the type of micro-instruction to be executed and the state of the minicomputer when the micro-instruction is to be executed. A microprogrammable processor port is provided to allow coupling of external hardware, e.g., I/O devices, other processors, etc., directly to the microprogrammed control processor. This capability is in addition to the standard input/output system of the minicomputer, thereby providing an alternate interface path for devices requiring very fast transfer rates. These devices interfaced through the microprogrammable processor port are directly coupled to the internal data busses of the minicomputer and addressed under direct microprogram control as if they were internal processor registers. Block transfers of data are provided via this microprogrammable port to allow transfers of large blocks of data without dependence on the I/O system timing of the minicomputer. A remote program load feature is provided whereby an I/O device or data communications interface can initiate a bootstrap operation in a remote computer, i.e., the computer can be halted, a preselected ROM loader program is transfer into memory, all input/output instructions in the loader are automatically configured to the proper select code of the I/O device, and the computer is restarted at the proper loader program starting address.

Transparent tri state latch

Abstract: Tri state logic gates in series are disclosed for permitting the latching of information from a first circuit by enabling a second circuit at the time information from the first circuit becomes valid. At the start of the memory cycle the second circuit is disabled and the first circuit is enabled. The data in the memory will appear at the output of the memory circuit to be delivered to the computer. Data is latched and retained on the data output bus by enabling the second circuit which assumes the level that appears on its input when enabled. The first circuit may then be disabled to permit it to carry out other operations.

Programmable controller with limit detection

Abstract: of the Disclosure A programmable controller for sensing the status of sensing devices and controlling the state of oper-ating devices in accordance with a stored program includes a position encoder input module which receives position data. In response to instructions in the stored program, the position data from the input module is compared with an upper and a lower limit stored in the controller memory, and if the data lies outside the limits, the controller logic unit is forced to a false decision.

Main memory protective device

Abstract: PURPOSE: To secure the writing inhibition to the region containing the main memory regardless of the state of the key, by providing the writing control bit to the region to designate the inhibition of the writing. COPYRIGHT: (C)1979,JPO&Japio

Method of level sensitive testing a functional logic system with embedded array

Abstract: Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status

Computational Experience with a Sequencing Algorithm Adapted to the Tardiness Problem

Abstract: This paper summarizes computational experience with a generalized dynamic programming algorithm known as the Chain Algorithm. This algorithm is a general purpose procedure for solving sequencing problems, and in this study the procedure is adapted to the problem of minimizing total tardiness in the single-machine model. The results indicate that at the present state of the art, 50-job problems can normally be solved in a few seconds of computer time, although memory requirements may be extensive.

State–space formulation of linear circuits containing periodically operated switches

Abstract: The state–space formulation of linear circuits containing periodically operated switches requires one to obtain the state and output equations. Further, it requires one to obtain the switching equations where discontinuities in the state variables occur at a switching instant. A new method for the computation of the state and output equations is given. Further, a procedure is described to obtain the switching equations, in the most general form, at a switching instant. Examples are given to illustrate these methods in finding the state, the output and the switching equations.

Remote electric state tester

Abstract: A tester for determining the state of an electric circuit at a location remote from the circuit is disclosed. The tester includes a transmitter connected to the circuit to be tested which transmits a different output signal for each state of the circuit to be tested and a combination receiver-indicator which is responsive to the output signals as transmitted from the transmitter.

Programmable logic controller

Abstract: A programmable logic controller includes a plurality of input interfaces and a plurality of output interfaces for connection to industrial equipment such as automatic assembly equipment, textile machinery, materials handling equipment, and chemical processes. The input and output circuits can be randomly addressed as to their state through an eight bit bus, which connects in parallel with up to 16 groups of eight input and/output circuits. The controller includes groups of timers which are each manually adjustable as to the timing operation and which are sequentially addressed each time a timing function is called for by the program. The timers are designed to be cascaded in groups to virtually any number of timers. The controller includes a scratch pad memory, half of which retains memory upon power failure and half of which does not. The control of the controller by the operator is made more nearly foolproof by interlocking the operations of control switches. Three programming instructions are available which are conditional upon the data in the accumulator of the controller.

Electronic pattern control for a sewing machine

Abstract: A logic circuit generates in succession the stitch-control data for the successive stitches of a selected stitch pattern. The logic circuit does not store simultaneously all the stitch-control data for all the stitches of all the selectable stitch patterns, in the way done by conventional addressable random-access stitch-pattern memories. Instead, the logic circuit assumes successive states, in response to successive machine-synchronized pulses. In each state it generates, in the sense of bringing into existence for the first time, stitch-control data for the next stitch to be produced, this stitch-control data being derived from data related to a preceding stitch, e.g., the stitch-control data for the preceding stitch. The number of logic elements needed is low compared to that needed for a random-access stitch-pattern memory of the type storing all the stitch-control data for all the stitches of all the selectable patterns.

Digital data change-of-state detector

Abstract: This invention relates to electronic circuits that detect changes in digital data that occur on a parallel data bus. The data on the parallel input bus is fed to a memory register. In addition, each data bus is tied to a comparison circuit which compares the input data with the output data on the same bus. If the data is not identical, the comparison circuit changes state to provide a signal which may be used for updating the data.

Condition control system utilizing digital logic

Abstract: A condition control system which utilizes digital logic to respond to the state of the condition being sensed. The control system utilizes a condition responsive element that is energized from an alternating current source and controls a first alternating current type of amplifier. The output of the amplifier is compared with a periodically generated pulse or logic command in an S-R latch circuit which is made up of a pair of NAND gates in a cross-connected configuration. The digital logic is arranged so that an output transistor and relay are energized only when the system senses the presence of the desired condition thereby indicating that it is safe to energize associated equipment.

Test equipment for program control apparatus

Abstract: PURPOSE:The under-operation system state is monitored, and further program correction medium is provided. Thus, unsatisfactory state judgement and its correction can be performed in a short time for the tested system.

Multiple computer control system - allows separate computers to correspond using tri-state interface circuits between address and data buses

Abstract: A multiple computer system uses at least two computers that are coupled to give combined solutions. They have their separate address and data busses connected by a two way driving circuit. This circuit has three conditions to give information flow in a forward or reverse direction or no flow. Gates are provided between the read signal output of each computer and the stores of both computers as well as for the write signal outputs. Each gate consists of two tristate gates. When more than two computers are involved, an OR gate and decoder are used to ensure that the third computer does not interfere when data transfer occurs between the other two. 'HALT' and 'HALT received' and interrupt signals control the flow of information from one computer to the specially allocated store area of the other.

Memory control system

Abstract: PURPOSE:To increase the flexibility of the memory system by including previously the information to select the memory into the access order to be given to the memory and then giving the access through selection of the memories featuring the different velocities and possessing the independent address space. CONSTITUTION:Order register 1 consists of operation part 11 and address designation part 12; and the type of the order, the memory selection information and the memory address to receive access are stored into parts 11 and 12 each. Then the information of part 11 is decoded by decoder 2, and the fixed output state is secured for FF3 based on the memory selection information. At the same time, memory control sequencer 10 is started. On the other hand, the address given from address designation part 12 is applied to selection circuit 7, and the input is selected for memory 20 or 30 which features the different velocities according to the output state of FF3 and also possesses the independent address space. Then the sending timing is decided by sequencer 10 for the data to memory 20 or 30 according to the output state of FF3. And the data output of memory 20 or 30 is selected by selection circuit 9 at the reading time.

Switch state detector

Abstract: PURPOSE:To applyithe switch state detector in plural units to obtain the electric signal at the area where the explosion may take place, by using just one circuit and providing one safety holder.

Input*output control system

Abstract: PURPOSE:To reduce the instruction start time of input/output control device, by scanning and referring the inquiry memory before the end of operation of I/O is informed to CPU, and providing the means to store the content when inquiry is made CONSTITUTION:A scanning circuit II12 is started with a machine cycle and signal, and the input of a multiplexer MPX3, ie, the scanning of the content of an inquiry memory 1 is made before the information of CPU As a result, if at least one inquiry state is present in the memory 1, FF15 is set and the presence of inquiry is stored Thus, an AND gate 9 is closed and the input and output start instruction is waited After that, FF8 is set with the scanning end signal I of a scanning circuit I11, FF15 is reset with the output Q, the gate 9 is opened, the machine cycle start signal is formed, and the machine cycle start circuit 10 is started If no inquiry is made, FF15 is not set, the output Q of FF8 is 0, the gate 9 is opened, the I/O controller is immediately operated and the instruction start time is reduced

Operational display unit for logic circuit

Abstract: PURPOSE:To display without error at high speed with an light emission diode the operating state of logic circuit by flow chart.

Logical circuit and ic semiconductor

Abstract: Integrated injection logic circuits and semiconductor devices employing threshold functions. Multiple-collector input transistors have their collectors connected to the bases of one or more output transistors. The output transistors have different weighted levels of injection current. The switching states of the output transistors are functions of the number of and conduction state of input transistors to which the output transistor are connected and to the weight of the injection current associated with the output transistor.

Power System State Measurements for Transient Control Augmentation Using Digital Techniques

Abstract: Any strategy, considered reasonable for the control of transient modes which occur as the result of a major disturbance in a large electric power system, will require fast and reasonably accurate measurements of at least two states per machine, namely, rotor speed deviation and torque angle. Since any control strategy will probably require an on-line digital computer for decision, computation, and execution, minimal computation time for the determination of state is imperative. Such a computer based technique along with the pertinent hardware for implementation is presented in this paper.

Current hogging injection logic with self-aligned output transistors

Abstract: Improved integrated bipolar semiconductor structures and a method of fabricating same are disclosed. The logic circuit structures disclosed have enhanced density and speed power product. The teaching of the disclosed logic circuit structures includes utilization and extension of the known concepts of Current Hogging Injection Logic (CHIL) and Integrated Injection Logic (I 2 L). The disclosed method of fabrication includes a minimum number of process steps, where each step is well within the state of the art and does not contain critical alignment problems.

Detection, storage and reproduction circuit for change of state - has registers for actual and comparative states and has comparator with timing generator

Abstract: The change-of-state detection, storage and reproduction circuit has a comparator (8) which, when changes of state are detected and stored, transmits an output signal where the contents of the two registers (4, 9) are unequal. This output signal triggers a command to store the value of a counter (3), together with the content of the register for actual states, in an event memory (6). The signal also causes the content of the register for actual states to be transferred to the register for comparative states and the address counter (13) to be switched on by one step.

History and present state of machine translation

Abstract: In the quarter century of i ts existence machine translat ion has gone through several s tages as a scientif ic discipline. The 1950's and early 1960's were a t ime of formation of MT and enthusiasm for i t . These were years of the appearance of many working teams, the crea t ion of the f i rs t exper imenta l MT systems, and together wi th this the statement of many insufficiently sound evaluations and rash communicat ions. This period of growth not only led to the wide development of theore t ica l invest iga t ion in the f ie ld of MT and the const ruc t ion of a number of experimental systems, but a lso to the development of the f i rs t pract ical ly operat ing systems. In the USA in 1962 a dec i s ion was made to cons t ruc t an opera t ing MT sy s tem, and in 1964 under the cont ro l o f fore ign technology of the Air Force Foreign Technology Command began operation of the SYSTRAN system [46], effect ing Russian-English translation of scientific and technical texts with human postediting.

Nondeterministic Finite Automata

Abstract: Nondeterminism is an important abstraction in computer science It refers to situations in which the next state of a computation is not uniquely determined by the current state Nondeterminism arises in real life when there is incomplete information about the state or when there are external forces at work that can affect the course of a computation For example, the behavior of a process in a distributed system might depend on messages from other processes that arrive at unpredictable times wifrh unpredictable contents

Electronic traffic light control system - uses process timer with microprocessor having two memories

Abstract: The traffic light controller is of the type having a logic circuit which defines a series of orders relative to a sate of a traffic light It has a control units which actuate the requirements of the orders at the traffic light level Each logic circuit has a microprocessor having a control processing unit with first and second memories The memories are designed to contain operation data to be carried out by the central processing unit They also contain data necessary for the central processor to carry out the operations ordered A process timer feeds the central processor A circuit applies to the central processor actuating signals at a predetermined rate The processor reacts actuating signals whilst transmitting a series of new order of traffic light state to the respective control units