Showing papers on "State (computer science) published in 1980"

Asynchronous data transmission system with state variable memory and handshaking protocol circuits

Abstract: This disclosure relates to a system and method for realizing asynchronous sequential circuits in a manner analagous to the stored state method for synchronous sequential circuits. The circuit is a stored state circuit including a memory and an output register with an input line and an input request line coupled to the memory and the output register having an output data line and an output acknowledge line. A pulse generator is coupled to the input request line so as to generate a timing signal, for transmission to the output register, a fixed period of time after receipt of a request signal on the input request line. A request signal will not appear on the input request line until a data signal on the input data line has stabilized. Furthermore, an acknowledge signal will not be generated until a signal on the output data line has stabilized. In this manner, an asynchronous sequential circuit is constructed which allows for utilization of existing component parts and provides for hazard-free and race-free implementations.

Verifying network protocols using temporal logic

Abstract: Programs that implement computer communications protocols can exhibit extremely complicated behavior, and neither informal reasoning nor testing is reliable enough to establish their correctness. In this paper we discuss the application of program verification techniques to protocols. This approach is more reliable than informal reasoning, but has the advantage over formal reasoning based on finite-state models that the complexity of the proof does not grow unmanageably as the size of the program increases. Certain tools of concurrent program verification that are especially useful for protocols are presented: history variables that record sequences of input and output values, temporal logic for expressing properties that must hold in a future system state (such as eventual receipt of a message), and module specification and composition rules. The use of these techniques is illustrated by verifying a simple data transfer protocol from the literature.

Programmer's manual for MMLE3, a general FORTRAN program for maximum likelihood parameter estimation

Abstract: The MMLE3 is a maximum likelihood parameter estimation program capable of handling general bilinear dynamic equations of arbitrary order with measurement noise and/or state noise (process noise). The basic MMLE3 program is quite general and, therefore, applicable to a wide variety of problems. The basic program can interact with a set of user written problem specific routines to simplify the use of the program on specific systems. A set of user routines for the aircraft stability and control derivative estimation problem is provided with the program. The implementation of the program on specific computer systems is discussed. The structure of the program is diagrammed, and the function and operation of individual routines is described. Complete listings and reference maps of the routines are included on microfiche as a supplement. Four test cases are discussed; listings of the input cards and program output for the test cases are included on microfiche as a supplement.

Asynchronous event prioritizing circuit

Abstract: A prioritizing circuit is provided for arbitrating between asynchronously occurring memory access request and memory refresh request signals to a dynamic RAM memory module. The circuit includes a latch circuit (20), a latch control circuit (21), and priority logic (22). The latch circuit is responsive to the request signals and latches the state of both signals upon receipt of a strobe signal generated by the latch control circuit. The latch control circuit generates the strobe signal upon detection of the first access request signal transmitted to the latch circuit at a predetermined logic level. To arbitrate priority between request signals occurring substantially simultaneously, the priority logic includes a combinatorial logic network responsive to the outputs of the latch circuit for generating a grant signal corresponding to the request signal having the higher priority. A delay circuit (23) provides a delayed strobe signal input to the priority logic, so that the combinatorial logic is only enabled after an appropriate settling time.

Programmable sequential logic circuit devices

Abstract: The programmable sequential logic circuit device is constructed to sequentially form an output signal to an external circuit and the circuit state for the next operation in accordance with input signals applied from outside and the internal state of the circuit. The device includes a first logic array for producing product terms of the input signals, a second logic array for producing sum terms of the first logic array, a two-dimensionally arrayed flip-flop array and means for setting the state of the flip-flop array. The flip-flop array is arranged in a plurality of rows of stages each including a plurality of serially connected flip-flop circuits. The inputs of respective rows are connected to the outputs of the second logic array, the outputs of the setting means are applied to the inputs of respective stages and the outputs thereof are parallelly fed back to the first logic array.

Composite Parallel Counters

Abstract: A graphical representation is presented for parallel counters, i.e., multiple input combinatorial modules that count the number of inputs being in a given state (normally logic ONE).

Reduced power tristate driver circuit

Abstract: A tristate driver circuit is provided having a logic input signal, to produce a logic 1 output level or a logic 0 output level, and a float input signal, to produce float state operation. The circuit comprises a first logic gate powered by a first buffer switch, a second logic gate powered by a second buffer switch, an output driver having a first driver input from the output of the first gate and a second signal driver input from the output of the second gate; the first and second buffer switches dissipating the greatest circuit power during the circuit float state operation, and means, coupled to the first and second buffer switches and to the source of float signal input signal, for interrupting power to the first and second buffer switches responsive to onset of the float state operation.

Resynchronizing circuit for time division multiplex system

Abstract: The invention relates to input and output circuits for multiplexing equipment, especially the kind used in telephone systems where nominally identical clocking signals have natural deviations of timing (called "plesiochronous" signals). The invention uses the "justification" principle to ensure the clock synchronization of plesiochronous digital signals. A buffer memory, with independent writing and reading capabilities, is formed of two first in-first out or "FiFo" memories connected in series. The request signal for a "justification" is made when a connection is completed between an IR (Input-Ready) output of the second FiFo memory and an input SO (Shift-Out) of the first FiFo memory, if there is an undesirable phase shift between the input and output clocking system. A reading clock oscillator has a frequency which is governed by a governing signal, which depends, at least in part, upon the electrical state existing in the series connection between the IR output of the second FiFo memory and the input SO of the first FiFo memory. The receiving and demultiplexing system uses a similar buffer memory to extract any "justification" signals which were added on transmission. A phase-locked loop including a quartz-controlled oscillator controls the output clocking of the demultiplexer.

Composite logic analyzer capable of data display in two time-related formats

Abstract: A combined logic timing and state analyzer comprises an internally clocked, timing analyzer section receiving a first set of logic signals, and an externally clocked, state analyzer section receiving a second set of logic signals. The timing analyzer section samples the first set of logic signals, as well as the external clock signal associated with the second set of logic signals, at a rate determined by the internal clock pulses and stores the samples in a first set of memories. The state analyzer section samples the second set of logic signals at a rate determined by the external clock pulses and stores the samples in a second set of memories. Data introduction into the memories terminates when they are triggered, as in the event of a malfunction of the system being investigated. The logic analyzer further includes a display circuit for repetitively reading out the first and the second sets of memories and for causing a display device to visually present the output data of the first memory set in the form of a timing diagram and the output data of the second memory set in the form of a state table. The time relationship between the two display formats can be readily ascertained since the timing diagram includes a waveform, or other visual representations, indicative of the external clock pulses used for sampling the second set of logic signals.

A general steady-state analysis program ANASP for thyristor circuits based on adjoint-network approach

Abstract: Described is a new computer aided package program ANASP for computing the steady-state waveforms for any configuration of thyristor circuits Newton-Raphson method is used to compute the initial state which generates the steady-state waveforms For the efficient and accurate evaluation of the Jacobi an matrix the adjoint network is introduced into thyristor circuits containing power diodes and thyristors, and the method of sensitivity calculation is proposed Using the program implemented, it is shown through examples that the computational time is considerably reduced to deter mine the steady state

Call processor for a satellite communications controller

Abstract: A call processor is disclosed for a satellite communications controller, having a plurality of M voice ports, with an E lead input and an M lead output connected to each of a first subplurality of voice ports for rotary dial telephones, a tone digit interface connected to each of a second subplurality of voice ports which are dedicated to transducing a tone digit received from a multifrequency dialing telephone which is connected to one of a third plurality of voice ports. The third voice ports are connected by means of an intranodal wrap through a digital switch in the communications controller with the transducing circuits at the second voice ports so that the transducing circuitry can be shared among all of the third plurality of voice ports connected to multifrequency dialing telephones. The call processor employs a substantial amount of processing logic in the form of clocked control logic which is executed in a nested time slice operation. The call processor includes a timing circuit having a first output for generating N periodic logic intervals in M periodic port scanning intervals generated at a second output thereof. The call processor includes a port status buffer having an address input connected to the second output of the timer, for storing a plurality of M-PSB words. Each PSB word stores the current status of a corresponding one of the M voice ports as a control state, the E&M lead states, processor communication status, state time duration, and a dialing digit. The clocked control logic has an input register connected to a data output of the port status buffer for receiving the PSB words as they are accessed sequentially from locations in the port status buffer. The clocked control logic has a modulo N counter connected to the first output of the timer, for sequencing clocked logiccontrol operations having combinatorial logic block inputs connected to the input register and the modulo N counter. The clocked logic control operations are executed in response to the counter, to selectively modify portions of the PSB word. The selectively modified PSB word is then rewritten into the port status buffer at the location accessed by the second output of the timer. Incrementing and decrementing logic operating synchronously with the counter, selectively modifies the state time duration field and dialing digit field in response to the clocked logic control operations. After control states embodied in the clocked control logic have completed their function, the results of the operation are transmitted to the host processor to complete the call connection operations in the satellite communications controller. The use of clocked control logic which is shared on a nested, time slice basis among all of the M voice ports enables the call processor to handle a large number of calls simultaneously while relieving the host processor of the management tasks associated with carrying out these call processing functions.

Logic state analyzer

Abstract: A logic state analyzer stores into a data acquisition memory only state data meeting preselected qualification state criteria chosen to weed out state data not of interest among the totality of states occuring within a collection of digital signals. The data acquisition memory retains only the last m-many states stored therein. A selectable integer k, o≦k≦m, determines how many additional storage operations are performed for qualified state data following the detection of a preselected trigger condition. The actual number of states occurring in the collection of digital signals after the trigger condition but before the storage of the kth qualified data state can be many times the value of k. Qualifying the state data prior to storage allows a modest size data acquisition memory to do the work of a much larger memory and spares the user the task of sorting through much state data known not to be of interest. The preselected qualification criteria may include don't-cares in the definition of the qualification state, as well as the logical OR'ing of a plurality of such qualification states.

Microprogrammed information processing system having self-checking function

Abstract: An information processing system of the microprogram control type having a control storage is provided with an exclusive memory unit for storing only the address information of a microprogram stored in the control storage and an exclusive control circuit for reading a specific microprogram out of the control storage by the address information from the exclusive memory unit and executing the program read out. The exclusive control circuit operates when the information processing unit is an idle state to execute successively the micro-steps of the specified microprogram read out in accordance with the address information in the exclusive memory unit, thereby to verify the information processing unit.

Apparatus and method for digital combination of delta modulated data

Abstract: Apparatus and method for processing sound as delta modulated digital data bits. A speaker console communicates with a listener console through a central switching unit. Tri-state generators within the central switching unit convert bipolar data modulated speaker data to tri-state logic which is then multiplexed onto a bus. The bus is sampled by a plurality of listener modules of a majority detector unit according to desired speaker combinations and a majority output is thereby determined for each time slot. A data generator modifies a bipolar delta modulated idle waveform according to the state of the idle waveform and the historical output of a listener module, incrementing and decrementing a carry register and a borrow register in the data generator to reflect storage, insertion or cancelling of majority "ones" or "zeros". The combining logic of the data generator enables the central switching unit to produce a combined output having the initial speaker data bit rate.

Data bus fault detector

Abstract: An error detection circuit detects prolonged sequences of unchanged logic state in a data busing structure. The circuit generates a complementary two rail logic output from a pair of flip-flops. The circuit includes a comparator which compares the logic state of the data input from the bus with the output of one of the flip-flops, and which inputs alternate opposite logic states to that flip-flop as long as the data input exists for a time in the same logic state as the output of the one flip-flop during a cycle. The complementary two rail output changes every cycle to actively exercise the error detection circuit and prevent silent failures therein. The circuit is self-checking because internal failures yield non-complementary outputs.

Arithmetic logic unit arranged for manipulating bits

Abstract: A digital computer is arranged to process data through an arithmetic logic unit in response to instructions residing sequentially in an instruction register, each instruction requiring a single instruction interval for fetching data from a selected source in a store, processing the data in the arithmetic logic unit, and storing the result of processing the data into a selected destination in the store. Means are provided for moving a single bit from any selected one of a plurality of bit positions in the selected source to any selected bit position of a plurality of bit positions in the selected destination during a single instruction interval without affecting the state of any other bit of the selected destination.

Digital phase synchronizer

Abstract: A state clock provides a bilevel signal of frequency which is an even multiple of the frequency of an incoming digital signal. A plurality of latches are responsive to the state signal. The outputs of the latches go to corresponding inputs of a memory array, the outputs of which are a plurality of terminals equal in number to the binary bits of a word stored in each address of the memory array. One of the output leads of the memory array passes through one of the state latches and to the output circuit. The other outputs go to the state latches where they are stored temporarily. The state latches are set on the rising transition of the state clock, while an input signal latch is set on the falling transition of the state clock. In this way at each cycle of the state clock the phase of the output signal is compared to that of the input signal; and if it is different, a corresponding output word of the memory array is fed back to the input to select the new output word and the new output signal, the phase of which will be closer to the phase of the input signal.

Fail-safe control computer

Abstract: When control of a control program stored in a memory of a microcomputer runs wild and enters an otherwise unused memory location, an instruction written in the otherwise unused location returns the control to its start state.

Emergency informing system

Abstract: PURPOSE:To know the accurate position of the terminal unit by making the signal generating means corresponding to the set-up of the address memory double the signal generating means which informs the response of the fault sensor means and then securing the talking enable state after generation of the signals. CONSTITUTION:When start switch 1 provided at the terminal device is closed, 2nd start register 4 is set. And control circuit 5 is started by the output of register 4. Furthermore, automatic dial 6 is started by the output of circuit 5 to call out the sensor device by the telephone number of address memory 9 which is set previously. And circuit 6 is connected to office terminal L0 via switch circuit 7. At the same time, the call signal obtained via switch circuit 21 is applied to incoming circuit 22 at the sensor device, and circuit 22 starts answer circuit 25. Furthermore, signal sending circuit 24 is started to give the answering state to the circuit, and the output is sent to the terminal unit via switch circuits 25 and 21. The terminal unit applies the signal to signal sending circuit 10 via circuit 7 and hybrid circuit 8 and then to circuit 5. Thus the position of the terminal unit can be known accurately.

The Design of a Virtual Machine for Ada

Abstract: This document formally defines a virtual machine. The design of the instruction set and state components of the machine is based on a semantic analysis of the basic concepts of Ada. The result is a high-level machine especially suited to run Ada programs.

Picture display device

Abstract: PURPOSE:To obtain an easy-to-see picture display by giving relative 1/2-bit shift to the signal of one field to the picture signal of the oblique lines. CONSTITUTION:The picture signals equivalent to one field are stored in memory device 1, and the same picture signal is read out twice to one frame from device 1. At the same time, the gate signals to select fields I and II are supplied to terminals T1 and T2, and the output of dealy circuit 5a and OR gate 9 are delivered alternately. In other words, in the case of field I the output is delivered to terminal T0 via the route of 1H-delay circuit 2, shift register 3a and 1-bit delay circuit 5a each; while in the case of field II the route includes circuit 2 and register 3 but thereafter is branched off into three different lines according to the operations logic arithmetic circuit 4 plus AND gates 8a1-8a3 as well as based on the state of each bit of shift registers 3a and 3b, and thus the output is delivered through terminal TD with difference of -1/2-bit, 0-bit and +1/2-bit each in comparison with the delay time of field I.

Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders

Abstract: Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this correspondence, the implementation of pipelined binary parallel counters with networks of latched quaternary threshold logic full adders is described and compared with the implementation using networks of latched binary full adders. Since each signal variable in quaternary logic may assume four logical states, twice the informational content of a binary variable, an over 50 percent savings in the total number of intermediate signal variables required to implement the parallel counter results. With the new quaternary logic circuits we will employ, over 40 percent fewer transistors and resistors are necessary for the implementation of pipelined binary parallel counters. The combination of these two factors could provide significantly reduced die areas for integrated pipelined parallel counters.

Diagnosis system for information processor controlled by microprogram

Abstract: PURPOSE:To secure the early detection for the error by performing the diagnosis program in the time-division way and under execution of the control program. CONSTITUTION:The control program and the diagnosis program are carried out in the 6:2 ratio. The diagnosis program detects the error and then sets up the error display bit. While the control program examines the state of the error display bit and then informs the error occurrence to the higher-rank unit in case the error is detected. When Set P1 features logic ''1'', FF4 is set and then reset when Reset P1 features logic ''1'' each. With setting of FF4, control program execution timing T1 becomes logic ''1'', and the control program is carried out while signal T1 features logic ''1''. FF5 is set when Set P2 features logic ''1'', and thus diagnosis program timing signal T2 features logic ''1'' for execution of the diagnosis program.

Overload control system

Abstract: PURPOSE:To realize an exchange system which can detect easily and quickly the overload and furthermore can offer the stabilized service even at the overload time in the function dispersion type exchange system. CONSTITUTION:In addition to internal processor 1, channel system module 8 is provided to carry out the input/output process independently. And the signals are exchanged to input/output processor 85 within module 8. In such constitution, the state change of the circuit which is read by digital control signal device 82 carrying the control signal (state signal of circuit) on it for the specified channel of talking highway 81 within module 8 is detected by processor 85 and then classified into the wake-up and other factors to be written into main memory device 86. Processor 1 receives the control signal through interface circuit 87 to give supervisory for the call generation state as well as to give the control to the input process of processor 85 at the time of overload. In such way, the lowering of the service can be prevented for the call by the exchange at the overload time.

Control circuit for motor vehicle electrical equipment - uses addressed logic clocked signals controlled from microprocessor to perform selective switching functions

Abstract: The circuit operates headlamps, window winders, winkers etc. of motor vehicles. The circuit allows the normally complex wiring associated with these units to be simplified. The system is microprocessor based and uses clock controlled coded signals to command and test each unit. The signals to these units make up a repeated frame divides into fixed time spaces each frame successively presenting a constant number of data bits, the unit being address identified. The processor successively explores the state of each normally operated dashboard switch and associated unit, the state of each unit being presented by dashboard lamps to the driver. Data on faults etc. are loaded into a visual monitor register by the microprocessor for visual display.

Conflict Theory and Segregation Academies: Application and Refinement of Dahrendorf's Theory.

Abstract: FOOTNOTES.................. 146 BIBLIOGRAPHY................................................ 149

Course control unit

Abstract: PURPOSE:To shift the mobile body with conventional electronic computer, by providing the simple course memory individually corresponding to the simple course constituting the transportation path network and the interlock circuit consisting of the hard with logic circuit using fail safe element. CONSTITUTION:The simple course 1 constituting the transportation network is provided with the simple course memory 11 corresponding individually to the course and the interlock circuits 14a...14n and 15a...15n consisting of the hard wire logic circuit using fail safe elements, and the interlock circuits 14a...14n, 15a...15n collate that the each simple course memory 11 corresponding to the simple course 1 in the route selected is locked to the state of a given memory content, no mobile body is in existence, in the selected route and the incoming point is receivable to a given direction, and the route open signal permitting the movement of the mobile body is produced. Thus, even if there is any program error, and even if the interlock circuit is in failure, no route open signal is produced and the mobile body can always be moved sefely by using the conventional electronic computer.

A simulator for teaching computer architecture

Abstract: This paper describes the specification, implementation and use of a computer system simulator. The simulator project was begun as a result of teaching a second year undergraduate course in computer systems.It became apparent that students only fully appreciate the differences in computer architecture when they are able to have "hands on" experience. This simulator, which operates at the register transfer level, allows students to gain experience of many different architectures without recourse to many different computers. This experience, in the first instance, is gained by the students being able to run programs on the simulated computers and then investigating the state of the computer after each machine or micro instruction. The design of these teaching computers is chosen so that they demonstrate a particular architectural detail. Subsequently students can design their own computer systems and compare them with simulations of commercially available computers.

Transistor logic three state output device

Abstract: A TTL transistor logic tristate output device particularly suitable for common bus applications including transistor and diode means for feedback of a portion of current from any output load and from stray capacitances to drive the pulldown element to greater conduction and accelerate sinking of current from the output to ground during transition at the output from high to low potential, said transistor means also arranged to block paths from the output to ground through the enable gate when the output is in the high impedance third state. Means for blocking current flow from the output through the device to high potential is also described.

Communication control unit

Abstract: PURPOSE:To lessen the load of the hardware as well as to lower the cost per circuit through the multi-circuit service for the nonsynchronous-system multi-circuit communication control unit by providing the ACU (arithmetic unit) which is changed into the firmware. CONSTITUTION:At the transmission time, CPU1 sets the circuit number and the data necessary for the data transmission to RAM12 and then informs the setting to ACU11. ACU11 receives the information of RAM12 based on the indication given from ROM1 in the nonsynchronous mood and also delivers the data to control unit SIO opposing to the designated circuit. SIO converts the received parallel data into the serial data or the like to deliver it to the circuit. In this case, ACU11 checks whether the data is the control code or not through ROM2 and then memorizes the state of that time. And in case the data is the control code, it is informed to CPU1 through RAM12. The above procedure can be given to each circuit, and thus a multiple control is possible to each circuit via ACU11 and firmware ROM1. So is at the reception time.