Showing papers on "State (computer science) published in 1984"

Poker machine communication system

Abstract: A system for controlling the operation of electronically linked gaming machines which enables information to be transferred between machines and from each machine to a control unit. In particular, credits on a machine can be transferred to another machine and the credit state of each machine can be interrogated and adjusted from the central control unit.

A Switch-Level Model and Simulator for MOS Digital Systems

Abstract: The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open," "closed," or "indeterminate." Many characteristics of MOS circuits can be modeled accurately, including: ratioed, complementary, and precharged logic; dynamic and static storage; (bidirectional) pass transistors; buses; charge sharing; and sneak paths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and operates at speeds approaching those of conventional logic gate simulators. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS.

User Recovery and Reversal in Interactive Systems

Abstract: Interactive systems, such as editors and program development environments, should be explicitly support recovery facilities that permit a user to reverse the effects of past actions and to restore an object to a prior state. A model for interactive systems is presented that allows recovery to be defined precisely and user and system responsibilities to be delineated. Various implementation techniques for supporting recovery are described. Application of a general recovery facility to support reverse execution is discussed. A program development system (called COPE) with extensive recovery facilities, including reverse execution, is described. Keywords: recovery, reverse execution, undo, checkpoint, editor, programming environments.

Adaptive self-repairing processor array

Abstract: An adaptive self-repairing processor array comprising a plurality of identical processing cells arranged in parallel orthogonal columns and rows to form a two dimensional matrix, each of said cells in the array having logic means and a memory for storing a memory state. The first row of the cells in the array forms a parallel input to the array. The last row of said cells in the array forms a parallel output from the array. The cells in the intermediate cells rows between the first and last rows are coupled to at least one cell in a previous cell row. The logic means in each cell computes a new data value based upon the input or inputs from such previous row cells and its present memory state. Each cell is further coupled to at least one cell in the subsequent row of cells. The computed new data value is provided as an output to the coupled cell or cells in the subsequent cell row. Each of the intermediate row cells are coupled to immediately adjacent neighbor cells of the same row to supply the new data value to these neighbor cells and correspondingly receive computed new data values from these same cells. The logic means in each cell compares the new data values received from such neighbor cells with its computed new value and accordingly updates its memory state based upon the results of the comparison.

Synthesis of Communicating Finite-State Machines with Guaranteed Progress

Abstract: We present a methodology to synthesize two communicating finite-state machines which exchange messages over two one-directional, FIFO channels. The methodology consists of two algorithms. The first algorithm takes one machine M , and constructs two communicating machines M' and N' such that 1) M' is constructed from M by adding some receiving transitions to it, and 2) the communication between M' and N' is bounded and free from deadlocks, unspecified receptions, nonexecutable transitions, and state ambiguities. The second algorithm takes the two machines M' and N' which result from the first algorithm, and computes the smallest possible capacities for the two channels between them. Both algorithms require an O(st) time, where s is the number of states in the given machine M , and t is the number of state transitions in M ; thus, the methodology is practical to use.

Dual port memory circuit

Abstract: Dual port memory which enables consecutive access operations from an arbitrary address. The memory includes a memory array, a random access peripheral circuit for effecting random access to the array, a counter, a setting circuit for setting the counting state of the counter at an optional value, a selection circuit for consecutively selecting the array in response to the output of the counter, and a control circuit for advancing the state of the counter in response to a shift pulse.

Discontinuous optimization procedure modelling the run-idle status of plural process components

Abstract: A method of optimizing the operation of a process so that desired products are produced at minimum cost. The process has a plurality of process components, with each component having a run status and an idle status. The process has available more than one input and produces more than one output. The process is controlled by a computer which is provided with a mathematical model of the process, which model includes a model of each of its components. The model for each process component includes a logic variable, which logic variable can have only two values, 0 and 1, and which represent the run or idle status of each process component. The computer, when predetermined conditions arise, solves a mixed integer equation to determine the optimum state of the process at a given time to produce the desired outputs, at desired rates and at minimum cost; and, in doing so, determines the value of the logic variable for each component. When a change of status of a process component from run to idle or idle to run is required to place the process in its optimum state, control signals to cause such change of status of process components are applied to such components.

Circuit testing apparatus employing signature analysis

Abstract: Apparatus is disclosed for testing an electrical circuit by means of signature analysis. Responses to a sequence of test patterns from the circuit under test are supplied to a linear feedback signature register (LFSR) which produces a signature signal at its output representing its current state in dependence upon its prior state and the received response signal. A programmed read-only-memory is addressed by these state signals of the LFSR and produces, at its output, a logical "1" signal if the current signature represents a permissible state of the LFSR and a logical "0" if the state is not permissable. This checking occurs throughout and during the testing sequence in contrast to conventional signature analysis wherein the comparison only occurs at the end of the testing sequence.

Device for controlling the application of power to a computer

Abstract: Apparatus and method for monitoring the state of the phone line, directly or as reflected by signals from the modem, and controlling the application of power to a computer so that the computer is powered in response to an incoming call. The apparatus includes a controllable power switching element interposed between the power source and the computer's power input, and logic circuitry responsive to the state of the phone line or modem interface for controlling the power switching element. An alarm clock also controls the power switching element to power the computer up at a predetermined time.

Integrated circuit programmable cross-point connection technique

Abstract: A technique for programming connections of conductors that is particularly adapted to be implemented as part of an integrated circuit so that a number of connections internal of the circuit can be made from outside the circuit in order to customize it after fabrication. A specific arrangement of five switching transistors is particularly advantageous for each cross-point of two conductors to be connected together in one of many possible ways. The desired switching arrangement at each cross-point may be programmed by use of the same conductors being interconnected to carry control signals from outside the circuit to a memory associated with each cross-point switching circuit. While these memories are being programmed, each cross-point is temporarily forced to a desired state for communicating the control signals from outside the circuit to the memories.

Polygraphic encryption-decryption communications system

Abstract: A public-key system for encoding, or encrypting, digital data wherein at least two singular matrices of binary bits provide separate encrypting factors. Each matrix is a product of a common singular matrix and a differing non-singular matrix. These encrypting matrices are loaded in separate memory formats. A Vernam or one-time key consisting of blocks or sets of randomly-generated binary bits are loaded into an input shift register, and the state of each stage is coupled as an enabling signal to gates which read out rows of each of the two stored matrices. Groups of outputs from gates serving each of the matrices are combined via column arranged, exclusively-OR gates fed, in parallel, to a shift register. The output of one shift register forms an encrypted decrypting signal. The output of the other shift register is exclusively-ORred in the manner of a one-time key with the binary encoded plaintext to be encrypted. As thus encrypted, it is transmitted with the decrypting signal to the addresses. There, the decrypting signal is transformed by appropriate private-key inverses of the invertible matrix component of the encrypting signal, and then, as modified, it is exclusively-ORred with the text encrypted signal whereby the text is decrypted.

Evaluating variations on program slicing for debugging (data-flow, ada)

Abstract: Debugging and maintaining computer programs is a difficult and time consuming task. The traditional methods used by a programmer to understand a program such as reading program text, reading program documentation, ad hoc testing with different inputs, or dynamic tracing, often overwhelm the programmer with details that have nothing to do with what he wants to know. A solution to this information overload problem is to reduce the amount of detail a programmer sees by an application of data-flow analysis, program slicing, that can be used to transform a large program into a smaller one containing only those statements relevant to the computation of a given output. Debugging tools have evolved through three generations. The first generation of tools produced information such as core dumps and instruction execution traces in terms of the underlying hardware. The second generation of debugging tools, often called symbolic debuggers, produced program state and history information in terms of the programming language being used. A third generation of debugging tools that attempt to locate faulty statements for the programmer has begun to emerge. The goal of this thesis was to evaluate program slicing as a debugging tool. To evaluate slicing we built a visually oriented, source-language independent, third generation debugging tool called Focus that can interactively compute and display program slices of FORTRAN and Ada programs. Focus was evaluated by comparing debugging performance between two groups of graduate student programmers. We also developed a method for combining program slices, called program dicing, to identify likely locations for faults within a program slice. Program dicing was evaluated by first introducing random errors into correct programs and then using program dicing to isolate the now incorrect statement. We found that dicing could eliminate from 93 to 98 percent of program statements from consideration while debugging a 118 line program. A second evaluation of dicing was made by comparing debugging performance between two groups of experienced student programmers. We found a significant improvement in the time to locate a program fault for subjects using dicing.

A History of Louisiana, 1939-1945. (Volumes I and II).

Abstract: ........................................ v Introduction ...................................... vii CHAPTER I: LOUISIANA IN 1939: THE LEGACY OF HUEY LONG AND HIS ASSOCIATES . . . . 1 CHAPTER II: THE 1939-1940 LOUISIANA GUBERNATORIAL ELECTION........................ 34 CHAPTER III: SAM JONES AND THE BEGINNING OF REFORM (1940-1941)..................... 96 CHAPTER IV: THE CONTINUING BATTLE FOR REFORM (1942-1944)..................... 144 CHAPTER V: THE EMERGENCE OF JIMMIE DAVIS (19431944) . 187

Wired logic voting circuit

Abstract: A wired voting circuit is described providing an output which follows the majority of input logic levels according to the equation: F=AB+AC+BC. A non-inverting signal voting node (D) and an inverting signal voting node (E) comprise a first and a second collector of an odd number of input differential transistor pairs (30, 32, 34) wherein said nodes are formed by wiring all of said first collectors together at one signal node and by wiring all of said second collectors together at the other signal node. Each signal node is coupled to a differential input of an output differential transistor pair (36). Currents are steered by the state of input logic onto either of the signal nodes, depending upon the input logic signal level. The signal level at each voting node is proportional to the number of input differential transistor pairs that steer current to the voting node. The voting scheme employs an odd number of logic inputs (T, U, V), such that an odd number of currents (Ix, Iy, Iz) are steered to the voting nodes. Therefore, the signal level at a first voting node is never equal to that of the other voting node during a steady state condition; the signal level difference between the two voting nodes is indicative of the majority state of the input logic signals. An output differential transistor pair compares the signal level difference and translates it to voltage levels compatible with other signals in the system in which the invention is used. By providing redundant signal pathways, signal processing reliability is enhanced. Monolithic device yields are improved by providing for diagnosis of faulty signal pathways and elimination thereof.

Tutorial: Statistical considerations in computer simulation: the state of the art†

Abstract: The multiple response problem in simulation analysis refers to the statistical design and analysis of simulation experiments which output more than a single response variable, or measure of effectiveness. In this article, the multivariate response simulation model is defined and some historical solutions from the literature are discussed. Recent research into the use of multivariate statistical methods in simulation analysis is reviewed, including the statistical rationale for the use of these techniques, the advantage of using these methods in simulation output analysis, and a comprehensive survey of the simulation literature which has applied these procedures to date. The concept of multivariate response simulation metamodel, an auxiliary, analytic model which serves to aid in the interpretation of the simulation model, is also presented.

Synthesis of Digital Design from Recursive Equations

Abstract: From the Publisher: Applicative languages provide a fully abstract, mathematically natural notation for specifying algorithms. This book develops a new approach to digital circuit design that is founded on the tenets of applicative programming style and which sheds light on functional programming disciplines by exploring their use in a novel realm of implementation. The book defines a circuit description language that uses systems equations to state connectivity-systems that are, in fact, applicative programs that compute the logical behavior of the circuit described. An interpreter is then presented through which both specifications and target descriptions can be executed, allowing engineers to experiment directly with the design notation without having to translate into a simulation language or construct a physical prototype. This greatly facilitates informal verification of design refinements and the implementation of benchmark tests. Moreover, the target language stands alone as a vehicle for rapid prototyping when more traditional design methods are used. An introduction to program synthesis through transformation is included. The techniques discussed are later adapted to digital design synthesis. A formal model of digital behavior is defined and a connection established between functional specifications and digital descriptions. A central theorem gives the characterization needed to serve as a goal for transformation. Several short examples illustrate the basic approach from the formal and experimental points of view. A complex exercise in language-driven design shows how advanced programming techniques can be brought to bear on larger design efforts. And finally, the book defines aspecialized transformation system to address data flow. Steven D. Johnson is Visiting Assistant Professor in the Computer Science Department at Indiana University, where he received his Ph.D. This book is included in the ACM Distinguished Dissertation Series.

Protective relay system

Abstract: A protective relay system for protecting a power system includes a selection circuit, a comparing circuit, and a data processing unit The selection circuit time-sequentially switches a plurality of input signals having electrical quantities from the power system under control of the data processing unit and applies the input signals to the comparing circuit The comparing circuit applies to the data processing unit a discriminated output signal representing the result of the comparing of a level of a signal having an electrical quantity and obtained from the input signals to the comparing circuit with a reference level At a time point upon lapse of a time corresponding to an electrical angle of 90° of the input signal, for example, after the logical level of a first discriminated output signal corresponding to a first controlled state of the selection circuit has been changed, the comparing circuit produces a second discriminated output signal corresponding to a second controlled state of the selection circuit different from the first controlled state The data processing unit determines the level of a protection output signal according to a logical level of the second discriminated output signal

Information storing circuit using blown and unblown fuses

Abstract: A circuit for storing information by blown and unblown fuses has at least two fuses per bit and an information output circuit. The information output circuit discriminates between the state in which all the fuses are unblown and the state in which at least one of the fuses is blown, and provides an output in accordance with the result of the discrimination as stored information.

Redundant rows in integrated circuit memories

Abstract: Decoding apparatus for an integrated circuit memory having normal rows of memory cells and at least one selectively connectable redundant second row of memory cells for being connected in place of one of the first rows, said apparatus including: a redundant decoder connected to each of the at least one redundant row, the redundant decoder including a plurality of selectable connections for creating an address for each of the at least one redundant row; a control signal generating circuit for generating a control signal of a first state until an address is supplied to the memory and of a second state if any of the at least one redundant row is selected by the address; and, another decoder connected to receive the control signal from the generating circuit for controlling the normal rows in response thereto.

Data processing system with improved output function

Abstract: A data processing system having an improved output circuit which can set its output terminal optionally at a high impedance state and at a voltage clamped state in a standby mode. The system includes an output circuit capable of setting the output terminal at the high impedance state and the voltage clamped state in response to a first control signal and a second control signal, respectively.

Numerical control machine tool

Abstract: PURPOSE:To know an operation state of a numerical control machine tool in an optional time band by using a means which contains a memory to store and the operation record information on the machine tool and delivers the stored record information. CONSTITUTION:A display 5, a keyboard 6, a processing memory 7, etc. are connected to a main control part 2 of a numerical control machine tool 1 via a bus line 3. While a mechanism part 13 is connected to a shaft control part 11. In a processing mode the part 2 delivers a processing command to the part 11 by a program PRO stored in the momory 7 and according to a processing start command MS of an operator given from a keyboard 6, etc. The part 2 monitors the processing execution state of the part 11 and the processing information MI on the processing time points, the number of works processed, etc. are stored to an operation record buffer memory 9 in the form of the operation record information DIR. The alarm information and the processing information produced in an operation mode are delivered optionally by a hard copy output means such as a printer 10, a tape puncher 12, etc.

Disk reproducing device

Abstract: PURPOSE:To reproduce a desired information signal, by reproducing a disk in which a signal obtained by adding a program discriminating signal to the head is recorded, and operating a reproducing apparatus by a program discriminating signal separated from said disk. CONSTITUTION:As for a signal recorded in a disk, a period signal is added to the head of an information data, and thereafter, a program discriminating signal ID1 and ID2, and an address signal AD are added. The signals ID1, ID2 are separated by a discriminating signal separating circuit, and are supplied to a comparing circuit 8 through a serial parallel converting circuit 7. In case when a designated data from a keyboard 9, which is supplied to the circuit 8 is A, the signal ID1 and the accompanying signal ID2 are supplied only to a decoder 3 only in case when the signal ID1 in a reproducing signal is A. The decoder 3 becomes an operating state when the discriminating signal is inputted, and processes its subsequent digital audio signal.

Method and apparatus for reporting dangerous conditions

Abstract: Attorney's Docket 7337 CAN INVENTORS: ALAN PAUL TROUP et al INVENTION: METHOD AND APPARATUS FOR REPORTING DANGEROUS CONDITIONS ABSTRACT OF THE INVENTION In an alarm system a central signal station periodically transmits interrogation signals, preferably in the form of infrared radiation packets to remotely located detectors which transmit a response signal back to the central signal station after differing time delays that are characteristic for the individual detectors and which permit the localization of the source of the response signal. In an alarm state, the detectors respond to every interrogation signal, in the normal operational state to only every mth interrogation signal, i.e. less often, and in a state of diminishing battery potential to only every small pth interrogation signal, i.e. even less often. The state of the individual detectors is determined from the frequency with which the response signals are transmitted back by the detectors, that is the ratio of the response signals to the interrogation signals. WWK:FR:rmw:mncl

Digital control system

Abstract: PURPOSE:To determine a control command matching with the purpose of control while evaluating the degree of attainment of the purpose according to the condition by estimating the current or future quantity of state when several predetermined control commands are outputted at the current time or a specific time later from the input to and the quantity of state of a controlled system. CONSTITUTION:A control command storage device 1 is stored with K past control commands U=(utI1-utIk) and an observation quantity storage device 2 is stored with J past state observation quantities Y=(htO1-ytOj). Then, arithme tic ai=f(Y,Yui) is performed by a predicting device 3 for an evaluation index A (e.g., speed after five seconds) corresponding to one control purpose of the controlled system on the basis of the past control command U, state observation quantity Y, and control command ui that a fuzzy control rule evaluating device 7 is to evaluate to obtain a forecasted value (s) of the evaluation index A. Similarly,a predicting device 4 for an evaluation index B calculates a predicted value bi of the evaluation index B from bi=g(Y,Y,ui).

Random pattern lock and key fault detection scheme for microprocessor systems

Abstract: A microprocessor-based electronic control unit utilizes a random pattern lock and key failure detection scheme to detect failures in the system being controlled or the control unit itself. The microprocessor system is programmed to receive a random data word, to output the same data word, and to perform a variety of tests which result in the generation of a data stream having a particular relationship to the random data word such that the data stream and the random data word bits can be combined to form a predetermined data word that is needed to maintain microprocessor control of the associated electrical system. If the microprocessor fails to generate a data stream which results in the formation of the proper predetermined data word, the control unit output will be locked into a predetermined state.

Inverter control circuit

Abstract: A circuit for controlling an inverter which derives an alternating current output by driving complementarily two switching elements serially connected to a direct current power source into switching operation. It is required for one of the switching elements to turn on while the other of the switching elements turns off, and such a state as two transistors turn on concurrently must be avoided. For this reason, a control signal to be applied to the switching element of the inverter is passed through a delay circuit. According to the present invention, the delay circuit is comprised of a counter and a logic circuit, wherein the counter is supplied with clock pulses and at the predetermined count value the counter is made to generate an output. Upon generation of the output, a control signal is made to be supplied to the switching element of the inverter through the logic circuit.

Operation mode setting apparatus on a single chip microprocessor

Abstract: On a single chip microprocessor which has 2 n operation modes, apparatus which permits selecting one mode out of the 2 n operation modes by using only one external pin connection and user program execution. A mode-setting register on the single chip microprocessor can be updated both through the external pin designating one of the two start modes, which are part of the 2 n operation modes, during the reset state of the microprocessor and through a write operation generated by executing a user program during the normal (nonreset) state of the microprocessor.

Method and apparatus for blanking noise present in an alternating electrical signal

Abstract: A noise blanking circuit for eliminating evidence of noise present :n an incoming alternating electrical control signal, such as a shaft encoder or tachometer signal in a servo control circuit, is disclosed. The alternating electrical signal is input to a first input (A) of a shift register (44) having a plurality of outputs (C, E, G, J). Clock signals having a preselected frequency are input to a second input (B) of the shift register (44) for digitally sampling the alternating electrical signal at the times of occurrence of the clock signals so as to produce digital samples shiftably stored in respective storage locations of the shift register (44), which are connected to the plurality of outputs (C, E, G, J) of the shift register. The digital samples appearing at predetermined ones of the plurality of outputs (C, E, G, J) of the shift register (44) are input to a logic circuit (50...60) for producing a first logic state (low state) as an output signal, when a first logic state appears at the predetermined ones of the plurality of outputs (C, E, G, J) of the shift register (44), and a second logic state (high state) as the output signal, when a second logic state appears at the predetermined ones of the plurality of outputs (C, E, G, J) of the shift register (44). The selectivity of the noise blanking circuit can be selected by adjusting the clock signal frequency and/or the number of storage locations included in the shift register (44) and/or changing the predetermined ones of the plurality of outputs (C, E, G, J) of the shift register (44) which are input to the logic circuit (50...60).