Showing papers on "State (computer science) published in 1987"

Instruction issue logic for high-performance, interruptable pipelined processors

Abstract: The performance of pipelined processors is severely limited by data dependencies. In order to achieve high performance, a mechanism to alleviate the effects of data dependencies must exist. If a pipelined CPU with multiple functional units is to be used in the presence of a virtual memory hierarchy, a mechanism must also exist for determining the state of the machine precisely. In this paper, we combine the issues of dependency-resolution and preciseness of state. We present a design for instruction issue logic that resolves dependencies dynamically and, at the same time, guarantees a precise state of the machine, without a significant hardware overhead. Detailed simulation studies for the proposed mechanism, using the Lawrence Livermore loops as a benchmark, are presented.

Avoiding the state explosion problem in temporal logic model checking

Abstract: 1. Introduction Many distributed programs can be viewed at some level of abstraction as communicating finite state machines. The dream of somehow using this observation to automate the verification of such programs can be traced all the way back to the early papers on Petri nets in the 1960's (1131, [lS]>. The temporal logic model checking procedure of Clarke, Emerson, and Sistia (16). [7], [20]) also attempts to exploit this observation. Their algorithm determines whether the global state transition graph associated with some concurrent program satisfies a formula in the temporal logic CTL. The algorithm is linear in both the size of the global state graph and the length of the specification and has been used successfully to find errors in network protocols and asynchronous circuits designs ([4]* 191, [17D. A number of other researchers have extended the basic model checking algorithm or

Special purpose neurocomputer system for solving optimization problems

Abstract: A network of N parallel processors are each one cross-connected to each other. Each cross connection includes a nodal weight delay circuit which carries status information as to whether a processor is "on" (=1) or "off" (=0) and whether its weighted influence (wij) is excitatory or inhibitory as between the two processors i and j on that cross connection. Additionally, the cross connection influence between a processor i and a processor j is time delayed with a selectively fixed set of machine cycles between any two processor i and j. A monitoring processor-controller senses when the majority of processors have achieved a stable non-changing state which will represent an optimum solution for a combinatorial problem.

In-system programmable logic device

Abstract: In-system programmable logic device which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells (455) such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine (520) which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin (470) receives serial input data which loads a shift register latch (505). The contents of the latch (505) are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit (530) is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.

Aggregation in Dynamic Programming

Abstract: Reducing the size of a dynamic program through state aggregation can significantly reduce both the data and the computation time required to solve a problem. We develop a new algorithm that combines state aggregation and disaggregation steps within a single-pass procedure. The solution obtained is automatically feasible for the original problem. By exploiting general conditions on the aggregate structure, we develop bounds for assessing the error from optimality introduced by the aggregation, and we illustrate with an application in infinite horizon optimization.

Fine Grain Concurrent Computations

Abstract: This thesis develops a computational model, a programming notation, and a set of programming principles to further and to demonstrate the practicality of programming fine grain concurrent computers. Programs are expressed in the computational model as a collection of definitions of autonomous computing agents called objects. In the execution of a program, the objects communicate data and synchronize their actions exclusively by message-passing. An object executes its definition only in response to receiving a message, and its actions may include sending messages, creating new objects, and modifying its own internal state. The number of actions that occur in response to a message is finite; Turing computability is achieved not within a single object, but through the interaction of objects. A new concurrent programming notation Cantor is used to demonstrate the cognitive process of writing programs using the object model. Programs for numerical sieves, sorting, the eight queens problem, and Gaussian elimination are fully described. Each of these programs involve up to thousands of objects in their execution. The general programming strategy is to first partition objects by their overall behavior and then to program the behaviors to be self-organizing. The semantics of Cantor are made precise through the definition of a formal semantics for Cantor and the object model. Objects are modelled as finite automata. The formal semantics is useful for proving program properties and for building frameworks to capture specific properties of object programs. The mathematical frameworks are constructed for building object graphs independently of program execution and for systematically removing objects that are irrelevant to program execution (garbage collection). The formal semantics are complemented by experiments that allow one to study the dynamics of the execution of Cantor programs on fine grain concurrent computers. The clean semantics of Cantor suggests simple metrics for evaluating the execution of concurrent programs for an ideal, abstract implementation. Program performance is also evaluated for environments where computing resources are limited. Prom the results of these experiments, hardware and software architectures for organizing fine grain message-passing computations is proposed, including support for fault tolerance and for garbage collection.

Programmable protocol engine having context free and context dependent processes

Abstract: In a programmable protocol engine, a core central processor implements a plurality of programmable finite state machines that perform context-dependent operations, and programmable satellite processing units that perform context-free operations. To assist in buffering the two way communications of the protocol engine, a memory is included which interacts with the central processor and the satellite units. The programmability of the protocol engine is achieved by realizing the satellite units with combinations of a processing unit and a memory unit which stores the instructions to be performed by the corresponding processing unit. The sequence of instructions to be performed is drawn from a small unique set of instructions which are adapted particularly to the tasks associated with protocol implementations. Instruction ports are provided for loading the necessary instructions to the satellite units and the central processor, thereby implementing a chosen protocol. To permit use of the protocol engine in environments where a plurality of users are multiplexed onto a single physical link, additional means are provided for storing the state of the finite state machines within the central processor, and for restoring the finite state machines to a previously stored set of states.

Emulation circuit for interfacing joystick to ROM cartridge slot of computer

Abstract: A circuit providing a joystick interface to a computer. The circuit plugs into the cartridge slot of the computer and receives power from the computer. The circuit includes an analog interface circuit, a read only memory (ROM) containing both a machine language program to drive the analog interface circuit, and a machine language application program. The analog interface circuit includes an analog-to-digital converter, a clock circuit, and a decoder. The circuit of the present invention also includes a tri-state bus interface circuit to communicate the state of input switches to the computer.

Method and apparatus for storing and forwarding voice signals and generating replies

Abstract: A system for storing and forwarding voice signals. The system provides for central, digital storage of voice signals for later access by addressee system users. When addresses access a previously stored voice signal they have the capability to incrementally construct a reply by "toggeling" between a playback state, to listen to the previously stored signal and a record state to record at least a partial response. In another embodiment originators of voice signals have the capability to edit signals after storage.

Control and data network

Abstract: A control and data network is described in which a number of access modules (10) having in each case one processor (14) with associated components (15) and in each case at least one input circuit (21) and one output circuit (17) for receiving and outputting data and signals are connected in parallel to a bus (11). The system exhibits a common control computer (12) which calls up the access modules (10) by means of addressed messages via the bus (11) and transmits data and control information and receives responses from the access modules (10). As a special feature, the access modules (10) have a control input (24) which, when a predetermined control signal is present, can bring the access module into a predetermined emergency stop state. The control inputs of the access modules in the network are connected to a common emergency stop control line (25) so that the entire system can be brought in a simple manner into an emergency stop state when disturbances or safety problems occur.

Programmable sequence generator

Abstract: A programmable sequence generator comprises a combinatorial logic matrix (10,12) and an on-chip timer (24) having count lines (26) coupled as inputs to the logic matrix (10). Combinatorial logic functions may be programmed into the matrix having as variables external inputs (14), a count number represented by the count lines (26) and internal inputs (48) fed back from outputs of he logic matrix (12). In a preferred embodiment, state registers (46) are provided, such that the programmable sequence generator can operate in any one of a plurality of different states. The programmable sequence generator can be configured as a waveform generator (92), a refresh timer (94) or a dynamic memory timing controller (96), among other programmable logic applications.

Semiconductor intergrated circuit device

Abstract: A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals

Memory system employing a zero DC power gate array for error correction

Abstract: An error-correcting memory system includes a storage module which receives an address during a read cycle and which reads data bits and check bits at the address, and it further includes a low DC power logic circuit which corrects errors in the data bits by decoding multiple minterms from the check bits; wherein the logic circuit is comprised of: a plurality of logic gates, one for generating each of the minterms by passing a constant power dissipating current to selectively decode the check bits; a control circuit for generating a control signal that is in one state during only a small fraction of the read cycle and is otherwise in an opposite state; and an enabling circuit, coupled between the control circuit and the logic gates, for enabling their selective decoding by permitting the constant current to flow through the gates only while the control signal is in its one state.

Principles of the Delphi parallel inference machine

Abstract: Many researchers have proposed using multiple communicating processors with a globally addressed memory for executing logic programs. However, the memory and communication contention issues characteristic of such designs have been neglected or palliated. In this paper we discuss a mew method for executing logic programs with low overhead on multiple processors. This method does not involve the sharing of memory or the copying of computation state between processors. We discuss the advantages of this approach over previous ones, and report progress on a multiprocessor implementation.

Circuit combining functions of cyclic redundancy check code and pseudo-random number generators

Abstract: A circuit is disclosed which combines the functions of a cyclic redundancy check code (CRCC) generator and a pseudo-random number generator in such a way that common elements are shared rather than duplicated. A 16-stage shift register and two linear feedback paths are included for the CRCC and pseudo-random number generators. A control section of the circuit controls the mode of operation of the circuit according to the state of a mode control signal. A signal on a clear line resets the shift register or initializes it with a selected value depending on the state of the mode control signal. The mode control signal also controls the input of data on a data line and the output of generated CRC and pseudo-random access codes on output lines.

Microprocessor timing emulator having a "Wait" state

Abstract: Within a test system for testing microprocessor-based systems, an apparatus for emulating the timing characteristics of a microprocessor, including when the microprocessor goes to a "WAIT" state during the execution of an instruction cycle A control signal RAM has a plurality of sets of instructions, each set being stored in a specific region, each set corresponding to the timing characteristics, that is the control, address and data signals, of a microprocessor A decode RAM stores coded instructions for addressing each region of the control signal RAM A sequence control RAM contains data for addressing each address location in the region of the control signal RAM selected by a signal input to the decode RAM In response to the combination of a clock signal and an external ready input signal, a sequence control latch supplies address signals to the control signal RAM to access a particular instruction of the selected instruction set and supplies the same signals to the address inputs of the sequence control memory The sequence control memory then latches the address signals for the next instruction in the sequence control latch The control signal memory stores data for producing a "WAIT" output A change in the external ready input signal suspends the instruction address sequencing and causes the control signal memory to produce the "WAIT" output

Semiconductor device having a test circuit

Abstract: A semiconductor device comprises a test signal generating circuit for generating a test signal having an arbitrary frequency, a first buffer for selectively outputting one of the test signal and an external input signal, at least one test circuit supplied with an output signal of the first buffer, an external output terminal, a logic circuit, a second buffer for selectively supplying to the external terminal one of the test signal from the test circuit and an output signal of the logic circuit, and a switching signal generating circuit for generating switching signals for the first and second buffers. The state of the test circuit is checked by use of the test signal to indirectly determine the state of the logic circuit.

Electronic locking system

Abstract: A field programmable electronic locking system includes a processor and an electrically erasable programmable read-only memory (EEPROM). The processor has address outputs electrically connected to address inputs of the EEPROM to address memory locations within the EEPROM, data inputs electrically connected to data inputs/outputs of the EEPROM to receive data from the EEPROM, and a high-impedence control input for transforming the address outputs of the processor to a high-impedence state. An EEPROM programmer activates the high-impedence control input of the processor to render the address outputs of the processor to a high-impedence state during a programming operation, and transmits address information and data to the address inputs and data inputs/outputs of the EEPROM, respectively during the programming information to write data into said EEPROM. Consequently, the EEPROM need not be removed from its socket or printed circuit board during programming, and may be programmed in the field.

Operator guidance by computer voice synthesizer

Abstract: A computer controlled by a voice input has a speech recognition section for converting a keyword of a program which is entered by the voice input and corresponds to a start number, thereby obtaining a digital code. The digital code data which indicates the keyword selects the start number corresponding to the storage content of a table stored in a program memory. The start number data is used to access a start address of the corresponding program, thereby starting and executing the program. Also disclosed is a system wherein when a chosen key of a key input device is operated while a voice operator guidance is generated, a key-in signal is produced to forcibly stop the ongoing guidance. In particular, when a plurality of voice operator guidances are provided, the computer learns the state of the operation by the operator from the manner of the forcible stop, and automatically stops the generation of the voice guidance on a specific item from the next processing.

Image recording apparatus with recording medium quanity detecting means

Abstract: An image recording apparatus such as a facsimile apparatus has a recorder, a control circuit, a display circuit, a sensor for detecting a quantity of remaining recording paper, and an auxiliary memory for storing data which has been received but not yet recorded due to short supply of recording paper. When image information is recorded in a divided manner or recording of image information is interrupted during reception of such information, this state can be displayed.

In-line scan control apparatus for data processor testing

Abstract: Apparatus is disclosed for generating pseudo-random bit patterns that are applied to a data processor, or other digital logic unit, for test purposes. In accordance with the invention, certain of the elemental storage units (e.g., flipflops) of the data processor are designed for two-mode operation: A normal mode of operation during which they operate as a part of the data processor in normal fashion, and a scan mode operation during which the elemental storage units respond to scan control signals to form a number of shift register or scan line configurations for receiving the pseudo-random sequenced or non-random sequenced test patterns generated by the apparatus. During testing, the bit patterns are passed through the scan line configurations and applied to compression circuits where, using cyclic redundancy checking (CRC), compression bit patterns received from the scan lines are achieved. Produced are test signatures that are stored in a memory for later comparison with standardized signatures to determine the PASS/FAIL condition of the processor. Tests can be preceded and followed by a controlled scan of the digital logic to save and restore the operational state of the digital logic. In this manner, test interruptions are relatively unobtrusive and essentially transparent to the logic tested.

Pseudo-static memory device having internal self-refresh circuit

Abstract: A pseudo-static memory device includes a memory cell array; a first access circuit for carrying out a sequential access to the word lines in the array to perform a refresh of cells; a second access circuit for bringing one of the word lines to an accessible state in response to an address signal; an access selection circuit for selecting either the first or the second circuit in accordance with an access precedence; a circuit for generating a control signal in response to a change in the address or a change in a level of an external clock; and a delay circuit for delaying the control signal by a predetermined time required for performing the refresh of cells. The second access circuit performs an address access in response to the delayed control signal irrespective of the operation of the first access circuit, thereby providing a greater allowance for an address skew and a considerable allowance for a lag or lead of the timing of the application of the address signal.

Semiconductor memory device with error correcting circuit

Abstract: A semiconductor memory includes a plurality of cell blocks, a refresh control circuit which sequentially refreshes a plurality of the cell blocks, an access control circuit which accesses a plurality of the cell blocks, and an ECC circuit which is provided in a data path between the access control circuit and the plurality of cell blocks, so that the data which is input from and output to the access control circuit is converted to a predetermined bit converted data (so called code) by the ECC circuit and is stored in the plurality of cell blocks. Accordingly, when the access control circuit accesses the plurality of cell blocks, if the access cannot be carried out for specified cell block which is in a refresh state (that is, a correct data (code) cannot be written to or read from the cell block in a refresh state) the data in the access control circuit side can be reproduced as correct data by the ECC circuit. Therefore, viewed from the external, a predetermined access can be carried out without being affected by the refresh state.

A Microprogrammed Computer Simulator

Abstract: A software educational tool (ET) has been developed that enables students of computer architecture to simulate a wide variety of computers on a fixed microprogram-organized-hardware (MOH). The user defines a computer by using ET to enter the appropriate microprogram. Machine language programs (macroprograms) may then be entered and a simulation made of their execution on the computer defined by the microprogram. While the simulated run is occurring, the state of the underlying machine may be observed at any point of execution. A microstep/graphics run mode may also be used to present a color display of the data path section of the MOH after each microinstruction is executed. In this paper, the ET simulation program, the MOH machine, and a simple example of how ET is used are presented.

Gateway for use in load control system

Abstract: A gateway circuit which exchanges information between a leased-line information transmission system and a power line carrier information transmission system includes a control circuit which receives and formats information transmitted over the leased-line information system and a separate control circuit which receives and formats information received over the power line carrier system. The formatted information is provided to a third control circuit which buffers the information and converts between the leased-line format and the power line carrier format to enable signal exchange between the two information transmission systems. The general control circuit responds to load control commands generated by manual switches located on the control unit and to load control commands forwarded over the leased-line system. The general control unit also contains storage elements which maintain the operating state of electrical loads on the power line and only transmit control information when an operating state must be changed.

A power supply with a built-in microcomputer for use in a computer system

Abstract: A power supply for use in a computer system according to this invention has a one-chip microcomputer (19) having a built-in A/D converter. The microcomputer (19), which has a communication function, performs a power off sequence for a computer system (11) and a power off sequence for a hard disk drive built in the computer system, while communicating with the computer system. Further, the microcomputer (19) detects the voltage and current of a chargeable battery (7), dis­criminates a low battery state, monitors a power switch (13), a hard disk drive switch (15) and a reset switch (17), and monitors an input/output voltage.

Terminal communications circuit

Abstract: A terminal communications network that provides communica­tion through a bus interface circuit to a network bus in accordance with the predetermined communications procedure, the terminal communications circuit (100) including a communica­tions interchange circuit (132) that exchanges protocol signals with the bus interface circuit in response to commands received from a signal state controller that is resident in the ter­minal. The communications interchange circuit (132) further provides communications state change information to the signal state controller to indicate the contents of the protocol signals from the bus information circuit. The signal state controller executes one of a plurality of program states to control communications over the network bus in accordance with predetermined communications procedure by providing commands to the communications interchange circuit in accordance with the program state that the signal state controller is currently executing. The signal state controller changes the program state in response to the communications state change informa­tion from the communications interchange circuit. Also pro­vided is a single command from the signal state controller to the communications interchange circuit that results in the communications interchange circuit providing a multiple of individual protocol signal patterns to the bus interface circuit enabling multiple communications procedures to be performed on the communications network with a single command from the signal state controller.