Showing papers on "State (computer science) published in 1988"

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations

Abstract: The problem of state assignment for synchronous finite-state machines (FSM), targeted towards multilevel combinational logic and feedback register implementations, are addressed. The authors present state-assignment algorithms that heuristically maximize the number of common cubes in the encoded network to maximize the number of literals in the resulting combinational logic network after multilevel logic optimization. Results over a wide range of benchmarks which prove the efficacy of the proposed techniques are presented. Literal counts averaging 20%-40% less than other state-assignment programs have been obtained. >

An improved protocol reachability analysis technique

Abstract: An automated analysis of all reachable states in a distributed system can be used to trace obscure logical errors that would be very hard to find manually. This type of validation is traditionally performed by the symbolic execution of a finite state machine (FSM) model of the system studied. The application of this method to systems of a practical size, though, is complicated by time and space requirements. If a system is larger, more space is needed to store the state descriptions and more time is needed to compare and analyze these states. This paper shows that if the FSM model is abandoned and replaced by a state vector model significant gains in performance are feasible, for the first time making it possible to perform effective validations of large systems.

Hot extraction and insertion of logic boards in an on-line communication system

Abstract: A real-time, high uptime transaction processing system includes many user terminals communicating with service providers via a communications network. A defective logic board is replaced or a board providing system expansion is installed without powering down the system by providing external auxiliary voltages and a reset signal to the board to put it in a passive state while it is being plugged into or unplugged from its backplane connector. Also under computer control the system is made inactive for a short period of time.

System and method for interfacing computer application programs written in different languages to a software system

Abstract: A support system and method for interfacing of computer application programs written in a plurality of languages to a software system such as a database manager of the like. A plurality of generic application program interfaces or entry points are defined having a corresponding plurality of parameters in a consistent form required by the system to execute functions. The parameters are transformations of like parameters associated with the application programs which call the APIs. Processor states corresponding to threads in the application programs are stored in a table shared by the generic APIs. Upon return from the call and execution of the system function, processor state is restored and control returned to the application program. Necessity for separate entry points for applications written in each different supported language is thereby avoided as well as associated increased development effort, maintenance, and support.

Programmable controller with parallel processors

Abstract: A programmable controller suitable for operating a machine to carry out programmed functions includes a plurality of program processors. Each of the program processors being operable to execute simultaneously a different user control program that directs the operation of the machine to perform specific functions. Each of the processor means is contained within a separate module which also includes a memory for storing the user control programs that are to be executed by that processor means. A mechanism is also provided to control the sequence in which the user control programs are executed and which of the processor means executes a given control program. At least one input/output interface circuit controls the gathering of data from various external sensors and in response to output data received from the processor means, controls the operation of actuator devices on the machine. The input/output data regarding state of the sensors and actuator devices are stored in a memory within the interface circuit. A system controller supervises the interaction and intercommunication of the plurality of processor means and the input/output interface circuits.

Multiple array customizable logic device

Abstract: Disclosed is an integrated circuit having multiple programmable arrays providing customizable logic. The integrated circuit has at least a first programmable array receiving a plurality of first inputs and generating a plurality of first outputs as programmed by the user. Also, it includes a second programmable array receiving a plurality of second inputs and generating a plurality of second outputs as programmed by the user. A means for selectiving interconnecting the inputs and outputs from the first and second programmable arrays is provided so that the programmable signals generated can be selectively connected in series, in parallel, or in a combination of series and parallel. Also provided are buried state registers for storing signals as programmed by the user. The stored signals from the buried state registers are likewise selectively interconnected with the input signals and output signals to provide added flexibility and power for the logic designer utilizing the device of the present invention.

Computer Engineering: Hardware Design

Abstract: PART I. 1. Binary Numbers and Codes. 2. Digital Circuits. 3. Combinational Systems. 4. Sequential Logic. PART II. 5. Registers and Counters. 6. Memory and Programmable Logic. 7. Register Transfer and Computer Operations. 8. Control Logic Design. PART III. 9. Computer Instructions and Addressing Modes. 10. Design of a Central Processing Unit (CPU). 11. Input-Output and Communication. 12. Memory Management. Index.

Semiconductor memory device

Abstract: PURPOSE:To omit the complicated control of addresses and to form a semiconductor memory into a single chip by providing a circuit which decides the coincidence between the write and read addresses and a generating circuit which produces a signal to inhibit a writing or reading within a single chip. CONSTITUTION:An address coincidence deciding circuit 4 reads an address 105' sent from a write address generating circuit 21 and an address 106 stored in a read address generating circuit 22 and sends the deciding result 107 showing the coincidence or discordance of both addresses to a write-read inhibiting signal generating circuit 5. The circuit 5 judges that a writing mode is presently set from a fact that a write instruction 101 is enable and then delivers a write inhibiting signal 108 in case the the result 107 shown a coincident state. Then the circuit 5 informs outside that data are written to all memory capacities and inhibits the subsequent writing actions. The data can be successively read and written with no address given from outside and at the same time the signal that inhibits the access of a device is outputted to outside. Thus the complicated address control is not needed.

Portable electronic equipment

Abstract: PURPOSE:To eliminate an excessive write operation, and to prolong a physical service life as a memory, by detecting the data length of the storage data at the time of inputting a storage data string, and deciding whether or not all of data constituting the storage data string can be stored in an area to be stored CONSTITUTION:At the time of writing the storage data in the area, when a control element 15 decides that all of inputted storage data are impossible to be stored in the area, according to data string byte number information in an instruction data, the control element 5 outputs a response data which means a byte number information error, then a state is returned to an instruction data waiting state When it is decided that the are possible to be stored, the control element 15 checks the data string byte number information, and the number of bytes constituting the data string included the instruction data in such case, and when the value of the former is larger than that of the latter, the control element 15 outputs the response data which means the byte number information error, then the state is returned to the instruction data waiting state In a case of other than the above case, the value of the latter is subtracted from that of the former and a result is held as a residual quantity

Semiconductor memory device

Abstract: PURPOSE:To eliminate the need to execute an address management whose processing is complicated, by adding a code data for showing an attribute, to a holding data, and generating an address by this code data CONSTITUTION:A selection of four modes of storage, read-out, retrieval and erasion of a data is executed by writing the information of 2 bits in a code register 2 In the code register, a code data and mode selecting information are contained, and also, write of the code data to the code register 2 is executed irrespective of a signal on an element selecting terminal CS A code comparator circuit always compares the code data in the code register 2, and a code data of a data which has been held in a main memory circuit 6, and gives its result to an address generating circuit 7 A controlling circuit 10 receives an effective signal of the element selecting terminal CS and shifts a memory device to a usable state

Semiconductor memory device

Abstract: PURPOSE:To prevent wrong destruction of data and security leak in a semiconductor memory independently of a microprocessor by providing a comparing means which compares the password of the memory with that of a latch to set or inhibit a prescribed mode in the semiconductor memory. CONSTITUTION:When the input password coincides with the set password, a read control signal is outputted from a comparing circuit 8 to an output line 15 and a semiconductor 4 is to the readable state. This read control signal is supplied to a control circuit 3 also and it is judged that data read is permitted. The control circuit 3 sends an address signal to the semiconductor memory 4 through an address bus 11 and reads desired data from the semiconductor memory 4 through a data bus 10. If the input password does not coincide with the set password, the comparing circuit 8 does not output the read control signal because a flag of 'read inhibition' is stored in a password memory 7. Thus, the security of stored data is kept and destruction of stored data or the like is prevented.

Parallel logic simulation on general purpose machines

Abstract: Three parallel algorithms for logic simulation have been developed and implemented on a general-purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speedups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled-mode algorithm which achieves speedups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between speeds one to three times faster than the conventional event-driven algorithm using one processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors. >

Programmable logic device configurable input/output cell

Abstract: An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.

Algorithms for Automated Protocol Validation

Abstract: This paper studies the four basic types of algorithm that, over the last ten years, have been developed for the automated validation of the logical consistency of data communication protocols. The algorithms are compared on memory usage, CPU time requirements, and the quality, or coverage, of the search for errors. It is shown that the best algorithm, according to above criteria, can be improved further in a significant way, by avoiding a known performance bottleneck. The algorithm derived in this manner works in a fixed size memory arena (it will never run out of memory), it is up to two orders of magnitude faster than the previous methods, and it has superior coverage of the state space when analyzing large protocol systems. The algorithm is the first for which the search efficiency (the number of states analyzed per second) does not depend of the size of the state space: there is no time penalty for analyzing very large state spaces. The effectiveness of the new algorithm is illustrated with the validation of a protocol of a realistic size: the ANSI/IEEE Standard 802.2 for logical link control.

Memory circuit with extended valid data output time

Abstract: A memory device (10) having an asymmetrical delay circuit (34) in a data output path of the memory device (10) is disclosed. The memory device (10) employs a precharge circuit (28) to impress a precharge state in a read memory access cycle. The asymmetrical delay circuit (34) imposes a relatively slow propagation delay on data signals which transition toward this precharge state, but imposes a relatively fast propagation delay on data signals which transition away from this precharge state. Specific embodiments of an output portion (32) of the memory device (10) are presented to accommodate a high impedance state in an output buffer (38) during signal transitions and to accommodate various polarity precharge states.

In-system programmable logic device with four dedicated terminals

Abstract: An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retain a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.

Dual I/O macrocell for high speed synchronous state machine

Abstract: An improved architecture for and a method of operating a high speed synchronous state machine is disclosed having a programmable logic array receiving inputs from dedicated input registers and having an input/output macrocell which includes two state registers and two input registers, and two transparent latches and two feedback multiplexers. The outputs from the input registers are multiplexed through an input multiplexer and the input registers may be clocked at different input clock rates than the state clock which clocks the state registers.

Real-time control sequencer with state matrix logic

Abstract: A high performance, real-time control sequencer is disclosed which incorporates a unique state matrix logic. This real-time control sequencer performs rapid resolution of control processed state transitions and the required control actions as a function of detected external events and the current control process state. The control sequencer's micro-instructions present event and current state data as inputs to a state matrix logic and initiate state matrix operations. The state matrix, in turn, outputs data defining and initiating the next control process state, required process control actions to be performed by the control sequencer microcode, process status, and event response or control output data. The real-time, event-driven data processor invention provides greater flexibility for reconfiguring event patterns to be detected and responses desired. It provides for a faster resolution of control process state transitions and the required control actions, and it accomplishes this with a larger repertoire of event patterns and responses stored in a smaller memory area, than has been required in the prior art.

Scannable register/latch circuit

Abstract: A circuit is described for functioning as a transparent latch, a latch where the data is determined by the state of a data signal at the time a signal changes state, a D-type flip-flop, and a scan path element. The mode of operation of the circuit is determined by the condition of respective ones of a set of control signals.

Method and apparatus for estimating fault coverage

Abstract: Method and apparatus estimates fault coverage of a set of test vectors to be applied to a circuit containing sequential elements. The apparatus permits sequential elements to be represented as functional blocks rather than combinational circuits with feedback. This is accomplished by taking into account the external state of the sequential element during circuit simulation. The apparatus also takes into account high impedance as possible inputs and outputs.

Numerical solution of optimal control problems with state constraints by sequential quadratic programming in function space

Abstract: • A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers.

Apparatus for measuring the speed of an object with circuit for converting analog signals into logic signals and circuit for varying sensitivity

Abstract: The circuit comprises a comparator 1 fed by a quasi-sinusoidal signal delivered by a source 2 for converting the positive alternations of the signal into pulses acceptable by digital computing means. According to the invention, the circuit comprises a current source 7 selectively connectible to the circuit in order to vary its sensitivity and to thus enable an evaluation of the amplitude of the signal delivered by the source 2. Application to the diagnosis of the operating state of a variable reluctance sensor delivering a quasi-sinusoidal signal representing the speed of rotation of a shaft fitted in a motor vehicle.

Application of state silos for recovery from memory management exceptions

Abstract: To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers. The first execution segment receives control information when a new operand specifier or operation is decoded, and otherwise holds the previously received control information. A microsequencer issues a series of microinstructions for each specifier or operation having been decoded, and also issues a series of microinstructions in a fault routine when a fault occurs. The microsequencer is also provided with a state silo so that the normal sequence of microinstruction execution is resumed when the fault is corrected.

SURE reliability analysis: Program and mathematics

Abstract: The SURE program is a new reliability analysis tool for ultrareliable computer system architectures. The computational methods on which the program is based provide an efficient means for computing accurate upper and lower bounds for the death state probabilities of a large class of semi-Markov models. Once a semi-Markov model is described using a simple input language, the SURE program automatically computes the upper and lower bounds on the probability of system failure. A parameter of the model can be specified as a variable over a range of values directing the SURE program to perform a sensitivity analysis automatically. This feature, along with the speed of the program, makes it especially useful as a design tool.

Survey of protocol verification techniques based on finite state machine models

Abstract: A survey is presented of techniques for verifying correctness properties of communications protocol design based on finite-state-machine (FSM) models. The conventional reachability analysis is first described, giving advantages and limitations. One major limitation is the so-called state-space explosion problem. To approach this and other problems, a survey of different approaches is presented. The author classifies the various techniques into categories. These include closed covers, localized protocol verification, divide-and-conquer, modified reachability analysis, and partial state exploration. Each technique is described in detail, including an analysis of its strengths and weaknesses. Based on this analysis, one technique is proposed as the basis for further work on a protocol verifier and analyzer workstation which is being designed as a protocol development tool. >

A method for efficiently executing Horn clause programs using multiple processors

Abstract: Previous investigations have suggested the use of multiple communicating processors for executing logic programs. However, this strategy lacks efficiency due to competition for memory and communication bandwidth, and this is a problem that has been largely neglected. In this paper we propose a realistic model for executing logic programs with low overhead on multiple processors. Our proposal does not involve shared memory or copying computation state between processors. The model organises computations over the nondeterministic proof tree so that different processors explore unique deterministic computation paths independently, in order to exploit the “OR-parallelism” present in a program. We discuss the advantages of this approach over previous ones, and suggest control strategies for making it effective in practice.

Protocol synthesis in a state-transition model

Abstract: The authors propose a protocol synthesis method in which both service and protocol specifications are based on a state-transition model. In particular, they present an algorithm for deriving the protocol specification from a given service specification which is described by a set of directly coupled finite state machines (FSMs). These FSMs together regulate the execution sequence of service primitives intended by the service specification. To complement the protocol derivation algorithm for dealing with error-prone communication medium, the authors also devise a transformation procedure to construct an error-recoverable protocol from its error-free version derived from the proposed algorithm. >

Networks and distributed computation: concepts, tools, and algorithms

Abstract: Networks and Distributed Computation covers the recent rapid developments in distributed systems. It introduces the basic tools for the design and analysis of systems involving large-scale concurrency, with examples based on network systems; considers problems of network and global state learning; discusses protocols allowing synchronization constraints to be distributed; and analyzes the fundamental elements of distribution in detail, using a large number of algorithms. Interprocess communication and synchronization are central issues in the design of distributed systems, taking on a different character from their counterparts in centralized systems. Raynal addresses these issues in detail and develops a coherent framework for presenting and analyzing a wide variety of algorithms relevant to distributed computation. Contents: First example - a data transfer protocol. Second example - independent control of logic clocks. Simple algorithms and protocols. Determination of the global state. Distributing a global synchronization constraint. Elements and algorithms for a toolbox. Michel Raynal is Professor of Computer Science at the Institute for Research in Informatics and Random Systems at the University of Rennes, France. He is author of Algorithms for Mutual Exclusion (MIT Press 1986). Networks and Distributed Computation is included in the Computer Systems series edited by Herb Schwetman.

High speed state machine

Abstract: A state element having a pair of parallel-connected, inversely-enabled latches forms the basic state-machine building block. A flip-latch is formed by combining this basic element with a multiplexer for selectively outputting alternate outputs of the latches. A litch-latch is formed by using the basic element alone with the two inputs fed from one of a pair of identical logic elements and feeding back the output from each latch to the logic element from which the input is not received. Other outputs of the logic elements are input into a multiplexer for alternately selecting the outputs from the respective logic elements to be the state machine output. These state elements function similarly to a flip-flop but generally produce less propagation delay and require a lower clocking signal frequency for a given state frequency.