Showing papers on "State (computer science) published in 1990"

A Stubborn Attack On State Explosion

Abstract: The paper presents the LTL preserving stubborn set method for reducing the amount of work needed in the automatic verification of concurrent systems with respect to linear time temporal logic specifications. The method facilitates the generation of reduced state spaces such that the truth values of a collection of linear temporal logic formulas are the same in the ordinary and reduced state spaces. The only restrictions posed by the method are that the collection of formulas must be known before the reduced state space generation is commenced, the use of the temporal operator “next” is prohibited, and the (reduced) state space of the system must be finite. The method cuts down the number of states by utilising the fact that in concurrent systems the nett result of the occurrence of two events is often independent of the order of occurrence.

The Complexity of Finite Functions.

Abstract: Publisher Summary This chapter discusses the complexity of finite functions. A deterministic Turing machine consists of a finite control and a finite collection of tapes each with a head for reading and writing. The finite control is a finite collection of states. A tape is an infinite list of cells each containing a symbol. Initially, all tapes have blanks except for the first, which contains the input string. Once started, the machine goes from state to state, reading the symbols under the heads, writing new ones, and moving the heads. The exact action taken is governed by the current state, the symbols read, and the next-move function of the machine. This continues until a designated halt state is entered. The machine indicates its output by the halting condition of the tapes. In a nondeterministic Turing machine, the next-move function is multivalued. There can be several computations on a given input and several output values.

Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags

Abstract: A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

A trainable security system emthod for the same

Abstract: A security system comprised of a device for monitoring an area under surveillance. The monitoring device produces images of the area. The security system is also comprised of a device for processing the images to determine whether the area is in a desired state or an undesired state. The processing device is trainable to learn the difference between the desired state and the undesired state. In a preferred embodiment, the monitoring device includes a video camera which produces video images of the area and the processing device includes a computer simulating a neural network. A method for determining whether an area under surveillance is in a desired state or an undesired state. The method comprises the steps of collecting data in a computer about the area which defines when the area is in the desired state or the undesired state. Next, training the computer from the collected data to essentially correctly identify when the area is in the desired state or in the undesired state while the area is under surveillance. Next, performing surveillance of the area with a computer such that the computer determines whether the area is in a desired state or the undesired state.

Quartz: a tool for tuning parallel program performance

Abstract: Initial implementations of parallel programs typically yield disappointing performance. Tuning to improve performance is thus a significant part of the parallel programming process. The effort required to tune a parallel program, and the level of performance that eventually is achieved, both depend heavily on the quality of the instrumentation that is available to the programmer.This paper describes Quartz, a new tool for tuning parallel program performance on shared memory multiprocessors. The philosophy underlying Quartz was inspired by that of the sequential UNIX tool gprof: to appropriately direct the attention of the programmer by efficiently measuring just those factors that are most responsible for performance and by relating these metrics to one another and to the structure of the program. This philosophy is even more important in the parallel domain than in the sequential domain, because of the dramatically greater number of possible metrics and the dramatically increased complexity of program structures.The principal metric of Quartz is normalized processor time: the total processor time spent in each section of code divided by the number of other processors that are concurrently busy when that section of code is being executed. Tied to the logical structure of the program, this metric provides a “smoking gun” pointing towards those areas of the program most responsible for poor performance. This information can be acquired efficiently by checkpointing to memory the number of busy processors and the state of each processor, and then statistically sampling these using a dedicated processor.In addition to describing the design rationale, functionality, and implementation of Quartz, the paper examines how Quartz would be used to solve a number of performance problems that have been reported as being frequently encountered, and describes a case study in which Quartz was used to significantly improve the performance of a CAD circuit verifier.

Kaleidoscope: mixing objects, constraints, and imperative programming

Abstract: Kaleidoscope is an object-oriented language being designed to integrate the traditional imperative object-oriented paradigm with the less traditional declarative constraint paradigm. Imperative state changes provide sequencing while declarative constraints provide object relations. A variables as streams semantics enables the declarative-imperative integration. A running example is used to illustrate the language concepts—a reimplementation of the MacDraw II dashed-lines dialog box. The example is in three parts: the input channel, using imperative code to sequence through modes; the output channel, using constraints to update the display; and the internal relations, using constraints to maintain the data objects' consistency requirements. The last sections of the paper discuss views as a natural result of combining objects with constraints, as well as related and future work.

Graphical interfaces for monitoring ladder logic programs

Abstract: A menu-driven system for developing Man-Machine Interfaces (MMI) for use in the graphical monitoring of ladder logic programs executing in programmable logic controllers PLCs. The Man-Machine Interfaces graphically depict plant processes controlled by the PLC. Data from the PLC representing plant process events (flows, state changes, tank levels, etc.) are communicated to the Man-Machine Interfaces. A Development System provides a programmer's "tool box" for constructing the Man-Machine Interfaces. Ladder logic programs and databases associated therewith are imported and accessed by the Development System for use in the development of the Man-Machine Interfaces. A Runtime System provides an execution environment for the Man-Machine Interfaces. The Runtime System has the ability to access ladder logic programs during monitoring operations. A user can "hot-key" to the ladder logic program for trouble-shooting purposes.

Irredundant sequential machines via optimal logic synthesis

Abstract: It is shown that optimal sequential logic synthesis can produce irredundant, fully testable finite-state machines. Synthesizing a sequential circuit from a state transition graph description involves the steps of state minimization, state assignment, and logic optimization. Previous approaches to producing fully and easily testable sequential circuits have involved the use of extra logic and constraints on state assignments and logic optimization. Here it is shown that 100% testability can be ensured without the addition of extra logic and without constraints on the state assignment and logic optimization. Unlike previous synthesis approaches to ensuring fully testable machines, there is no area/performance penalty associated with this approach. This technique can be used in conjunction with previous approaches to ensure that the synthesized machine is easily testable. Given a state-transition-graph specification, a logic-level automaton that is fully testable for all single stuck-at faults in the combinational logic without access to the memory elements is synthesized. >

Optimized synthesis of self-testable finite state machines

Abstract: A synthesis procedure for self-testable finite state machines is presented. Testability comes under consideration when the behavioral description of the circuit is being transformed into a structural description. To this end, a novel state encoding algorithm, as well as a modified self-test architecture, is developed. Experimental results show that this approach leads to a significant reduction of hardware overhead. Self-testing circuits generally employ linear feedback shift registers for pattern generation. The impact of choosing a particular feedback polynomial on the state encoding is discussed. >

Semiconductor memory with improved test mode

Abstract: An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.

Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip

Abstract: A VLSI chip debug and production test apparatus that allows an engineer to view the state of hundreds of signals internal to a chip in real-time without probing, which greatly simplifies the isolation of circuit, speed, logic, and microcode bugs. For production testing, it also provides the ability to check the state of these internal signals on a clock-by-clock basis. The mechanism uses a gated XOR-input serial shift-register cell (10), which is stepped out underneath major buses in otherwise unpopulated areas of the chip. Several of these cell groups are linked together to form a scanout path of the desired length, the operation of which is controlled with a single input pin (40). Output data is channeled through a shared output pin (19) to a VLSI tester (16). In the tester (16) the data (19) is checked and accumulated by back-end software over multiple test-loop iterations, and formatted into a readable form.

Algorithms for automated protocol verification

Abstract: This paper studies the four basic types of algorithm that, over the last 10 years, have been developed for the automated verification of the logical consistency of data communication protocols. The algorithms are compared on memory usage, CPU time requirements, and the quality of the search for errors. It is shown that the best algorithm, according to above criteria, can be improved further in a significant way, by avoiding a known performance bottleneck. The algorithm derived in this manner works in a fixed-size memory arena (it will never run out of memory), it is up to 2 orders of magnitude faster than the previous methods, and it has superior coverage of the state space when analyzing large protocol systems. The algorithm is the first for which the search efficiency (the number of states analyzed per second) does not depend on the size of the state space: there is no time penalty for analyzing very large state spaces. The practicality of the new algorithm has been tested in the verification of portions of AT&T's 5ESS® switch. The models analyzed in these tests generated up to 250 million composite system states, that could be analyzed effectively in an hour's worth of CPU time on a large mainframe computer.

Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence

Abstract: A theory of sequential hardware equivalence [1] is presented, including the notions of gate-level model (GLM), hardware finite state machine (HFSM), state equivalence (∼), alignability, resetability, and sequential hardware equivalence (≈). This theory is motivated by (1) the observation that it is impossible to control the initial state of a machine when it is powered on, and (2) the desire to decide equivalence of two designs based solely on their netlists and logic device models, without knowledge of intended initial states or intended environments.

Method and apparatus to improve static path analysis of digital circuits

Abstract: The method of the present invention includes steps wherein a circuit designer, using standard computer assisted design (CAD) tools, designs a circuit which may include multi-cycle paths (MCPs). The designer inserts a conceptual circuit element, referred to as a "path breaker" into multi-cycle paths, such that the result is to convert all multi-cycle paths into single cycle paths. The designer then utilizes functional simulation software to edit the circuit design. To the simulator, a path breaker appears to be a latch in which the latch output goes to an unknown state when the input changes, and remains so until the output has been clocked and is equal to the input. Traditional logic synthesis is then performed on the circuit such that a net list is generated which includes the path breakers. Based on the net list, a post processor determines where in the circuit multi-cycle paths exist and generates a net list without path breakers, as well as a list of the multi-cycle paths. The list of multi-cycle paths is provided to a static path analysis program where the locations of the multi-cycle paths denote exceptions. Timing analysis is then performed, and if the circuit is satisfactory, fabrication may be completed using the net list without the conceptual path breakers.

Method and apparatus for deriving mirrored unit state when re-initializing a system

Abstract: A data processing system having a pair of mirrored storage units maintains a state record of the mirrored pair in system memory. In order to be able to determine state when the system is re-initialized, this state information is also stored on each storage unit of the mirrored pair, and in an alternate location. When the state changes, the operating system writes the new state to those storage units which are still functioning, and to the alternate location. In order to prevent ambiguous situations, only certain defined state transitions are permitted. When the system is re-initialized, it attempts to read the state information stored on the storage units. If either unit can not be read, the system substitutes the state retrieved from the alternate state record for the state that would have been read from the non-responding unit. This pair of states from the two units index an unique entry in a state derivation table containing the resultant state.

System for transforming user data in accordance with an algorithm defined by design data and for evaluating the transformed data against logical criteria

Abstract: A computer system for processing complex information representative of business transactions. Specifically, the system stores transaction data, which is then reversibly transformed in accordance with predetermined processing algorithms, while it is externally inaccessible. In this static state, the transformed transaction data is evaluated against predetermined logical criteria. The evaluation produces either successful or unsuccessful results. If successful, the transformed data is then made externally accessible. If unsuccessful, the original transaction data is made externally accessible.

Redundancies and don't cares in sequential logic synthesis

Abstract: The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a combinational circuit can be explicitly identified using test generation algorithms or implicitly eliminated by specifying don't cares for each gate in the combinational network and minimizing the gates, subject to the don't care conditions. In this article, we explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense, but may be redundant because they do not alter the terminal behavior of a nonscan sequential machine. These sequential redundancies result in a faulty State Transition Graph (STG) that is equivalent to the STG of the true machine. We present a classification of redundant faults in sequential circuits composed of single or interacting finite state machines. For each of the different classes of redundancies, we define don't care sets which if optimally exploited will result in the implicit elimination of any such redundancies in a given circuit. We present systematic methods for the exploitation of sequential don't cares that correspond to sequences of vectors that never appear in cascaded or interacting sequential circuits. Using these don't care sets in an optimal sequential synthesis procedure of state minimization, state assignment, and combinational logic optimization results in fully testable lumped or interacting finite state machines. We present experimental results which indicate that medium-sized irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times by exploiting these don't cares.

Neural network computer

Abstract: PURPOSE:To simulate a neural network of large scale at high speed by shortening computing time by omitting the computation and communication of a neuron set at a stable state earlier. CONSTITUTION:Plural neuroprocessors 1 are provided with means 7 to hold a past state, means 8, 4, 3, and 2 to compute a neuro model when receiving output from another neuroprocessor, and means 5 to output difference between a computed result and the past state. When the result of a differential value shows a figure other than 0, communication to another neuroprocessor is performed via a data bus 9 and an address bus 10, and also, the value at that time is held at the holding means 7. Such operation is repeated, and when all of the 0 detectors 6 in all neuroprocessors detect 0s, it means that the neural network is set at the stable state, then, the computation is completed. In such a way, it is possible to simulate the neural network of large scale at high speed.

Voice applications generator

Abstract: Apparatus and method for performing at least one voice related application, the apparatus including a state table memory 62 for storing information expressive of at least two states 64. The states are entered into the state table memory by a state generator 68 during interaction with a voice applications writer. Each of the states includes at least an identification of the state, an identification of an action to be performed by the execu­tion of the state and an identification for at least one state to be executed next upon a termination of the ac­tion. The apparatus further includes a state machine 60 for reading information expressive of a state from the state table memory and for invoking the identified action 66. The state machine includes an input for receiving a signal, or edge, from the invoked action indicative of a termination of the action and, responsive to the reception of the signal, determines the identification of a next state to be read and executed. Certain of the actions are actions which receive audio signals from or which transmit audio signals to a digital or an analog voice trunk cou­pled to a phone switching apparatus.

High-level language debugging for concurrent programs

Abstract: An integrated system design for debugging distributed programs written in concurrent high-level languages is described. A variety of user-interface, monitoring, and analysis tools integrated around a uniform process model are provided. Because the tools are language-based, the user does not have to deal with low-level implementation details of distribution and concurrency, and instead can focus on the logic of the program in terms of language-level objects and constructs. The tools provide facilities for experimentation with process scheduling, environment simulation, and nondeterministic selections. Presentation and analysis of the program's behavior are supported by history replay, state queries, and assertion checking. Assertions are formulated in linear time temporal logic, which is a logic particularly well suited to specify the behavior of distributed programs.The tools are separated into two sets. The language-specific tools are those that directly interact with programs for monitoring of and on-line experimenting with distributed programs. The language-independent tools are those that support off-line presentation and analysis of the monitored information. This separation makes the system applicable to a wide range of programming languages. In addition, the separation of interactive experimentation from off-line analysis provides for efficient exploitation of both user time and machine resources. The implementation of a debugging facility for OCCAM is described.

Sequential test generation at the register-transfer and logic levels

Abstract: The problem of test generation for non-scan sequential VLSI circuits is addressed. A novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented. Our approach is targeted at chips with data-path like STG.The problem of sequential test generation is decomposed into three subproblems of combinational test generation, fault-free state justification and fault-free state differentiation. Standard combinational test generation algorithms are used to generate test vectors for stuck-at faults in the logic-level implementation. The required state corresponding to the test vector is justified using a fault-free justification step that is performed using the RTL specification. Similarly, if the effect of the fault has been propagated by the test vector to the flip-flop inputs alone, the faulty state produced is differentiated from the true next state by a differentiation step that uses the RTL specification.New and efficient algorithms for fault-free state justification and differentiation on RTL descriptions that contain arithmetic as well as random logic modules are described. Unlike previous approaches, this approach does not require the storage of covers or a partial STG and can be used to generate tests for entire chips without scan. Exploiting RTL information, together with a new conflict resolution technique results in improvements of up to 100X in performance over sequential test generation techniques restricted to operate at the logic level. We have successfully generated tests for the viterbi speech processor chip [18].

MIS-MV: optimization of multi-level logic with multiple-values inputs

Abstract: Techniques are presented for the optimization of multi-level logic with multiple-valued input variables. The motivation for this is to tackle the input encoding problem in logic synthesis, where binary codes need to be found for the different values of a symbolic input variable. Multi-level multiple-valued optimization is used to generate constraints that are used to determine the codes. The state assignment problem in sequential logic synthesis can be approximated as an input encoding problem by ignoring the next state field, which is reasonable when the primary output logic, dominates the next state logic. A novel technique is presented for extracting common factors with multiple-valued variables, and it is shown how other multi-level optimization techniques are easily extended with multiple-valued variables. These ideas have been implemented as algorithms in the MIS-MV program. Practical issues are also presented regarding implementation. Experimental results are also given. >

System for registering data into a memory

Abstract: A system for registering data into a memory has memory means for storing a plurality of data in a predetermined form and retrieves the stored data for use in a desired process. The memory means is divided into a first area in which the data in the predetermined form is stored, and a second area. The data used in the desired process as well as frequency of use data are stored in the second area. The data stored in the second area is reused for the desired process, and the frequency of use data of that data is updated. When the frequency of use data reaches a predetermined state, the data is moved into the first area as formal registration data.

Radiation resistant sram memory cell

Abstract: A memory cell employs four interconnected modules, each having two inputs and a truth table that has a logic level for input states and provides for a high impedance output state for unallowed states which differ from an allowed state by the status of one input. The interconnection is such that each module of a pair has as inputs the outputs of both members of the other pair, so that if one module changes state, the inputs to the members of the other will be in one of the unallowed states that produces a high impedance output. Thus, a radiation induced change of state in one module will not propagate through the system, but will be restored to an allowed state by action of the unaffected modules.

Programmable logic device with observability and preloadability for buried state registers

Abstract: A device having a number of general registers each allocated an input/output port and a number of internal "buried" state registers. A user-controlled signal permits observation of the contents of the buried state registers at an input/output port although these registers are not allocated an input/output port. Each register is connected to a logic circuit internal to the device by a dedicated feedback path so that all registers can be used to specify states in a state machine sequencer. A fuse-programmable XOR gate permits a user to control generation of signals at the ports by permitting enabling and disabling of an inverting output buffer. Asynchronous reset and synchronous preset of the registers is provided. In addition to the dedicated feedback paths, programmable feedback paths are provided. An output inverter can selectably be enabled from internal signals or from an externasl pin. The input/output circuit can be deployed in banks, each bank selectably receiving the same or a different clock. The registers can be preloaded via an internally-generated signal or from the external pins. In an alternative embodiment, a programmable AND array and a pair of programmable OR arrays, each serving one of the banks, provides a flexible programmable logic array device with observable buried states.

Easily testable PLA-based finite state machines

Abstract: An outline is presented of a synthesis procedure that, beginning from a state transition graph (STG) description of a sequential machine, produces an optimized easily testable programmable logic array (PLA) based logic implementation. Previous approaches to synthesizing easily testable sequential machines have concentrated on the stuck-at-fault model; for PLAs, an extended fault model called the crosspoint fault model has been used. The authors propose a procedure of constrained state assignment and logic optimization which guarantees testability for all combinationally irredundant crosspoint faults in a PLA-based finite-state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a scan design methodology. Results are presented which show that the area/performance penalties in return for easy testability are small. >

Semiconductor integrated circuit device

Abstract: PURPOSE:To reduce a power consumption of an I L logic circuit part in a non-operation state by installing a current-value changeover circuit in a current source circuit used to supply a circuit current to the I L logic circuit part. CONSTITUTION:This device is composed of an integrated injection logic (I L) logic circuit part 1 and a current source circuit 2; the current source circuit 2 is constituted of a transistor Q1 and resistances R1, R2. When a current-value changeover signal VI is at a low level, the transistor Q1 is set to an ON state; a circuit current IC flowing to the I L logic circuit part 1 during this state is designated as IC1. When the current-value changeover signal VI is at a high level, the transistor Q1 is set to an OFF state; the circuit current IC during this state is designated as IC2; then, IC2 IC1XR2/(R1+R2). Accordingly, the circuit current can be changed over by a signal level of the current-value changeover signal V1; when the resistance R1 is increased, the electric current IC2 in the OFF state can be decreased. Thereby, it is possible to reduce a power consumption of the I L logic circuit part 1 in a non-operation state.

Noise tolerant input buffer

Abstract: An input buffer interface circuit (10) provides high state and low state input noise tolerance by a tri-state CMOS inverter (20) having high state and low state inputs (22,24) which are driven conditionally after the propagation of an input signal through predetermined high state and low state delay circuits. In one embodiment, a resettable high state delay circuit is provided by a cascaded combination of NOR gates and inverters, whereby the delay is preempted automatically by an excursion from high to low with the result that the delay path is reinitialized automatically for rejection of successive high state ringing fluctuations. A resettable low state delay circuit is provided by a cascaded combination of NAND gates and inverters.

Regelsystem fuer kraftfahrzeuge

Abstract: A combined control system for motor vehicles is essentially composed of sensors and electronic circuits which evaluate the signals from the sensors and which generate control signals for controlling anti-locking or anti-skid subsystems, level and/or chassis control subsystems and so on. The combined control system is provided with an interactive state observer which receives signals from the circuits, transmits signals to the circuits and generates at predetermined moments signals which place one or several control subsystems in a defined state in a short time. In this state, vehicle constants or data are determined from the sensor signals and their modifications and are taken into account as updated control data.