Showing papers on "State (computer science) published in 1992"

Symbolic model checking: an approach to the state explosion problem

Abstract: Finite state models of concurrent systems grow exponentially as the number of components of the system increases. This is known widely as the state explosion problem in automatic verification, and has limited finite state verification methods to small systems. To avoid this problem, a method called symbolic model checking is proposed and studied. This method avoids building a state graph by using Boolean formulas to represent sets and relations. A variety of properties characterized by least and greatest fixed points can be verified purely by manipulations of these formulas using Ordered Binary Decision Diagrams. Theoretically, a structural class of sequential circuits is demonstrated whose transition relations can be represented by polynomial space OBDDs, though the number of states is exponential. This result is born out by experimental results on example circuits and systems. The most complex of these is the cache consistency protocol of a commercial distributed multiprocessor. The symbolic model checking technique revealed subtle errors in this protocol, resulting from complex execution sequences that would occur with very low probability in random simulation runs. In order to model the cache protocol, a language was developed for describing sequential circuits and protocols at various levels of abstraction. This language has a synchronous dataflow semantics, but allows nondeterminism and supports interleaving processes with shared variables. A system called SMV can automatically verify programs in this language with respect to temporal logic formulas, using the symbolic model checking technique. A technique for proving properties of inductively generated classes of finite state systems is also developed. The proof is checked automatically, but requires a user supplied process called a process invariant to act as an inductive hypothesis. An invariant is developed for the distributed cache protocol, allowing properties of systems with an arbitrary number of processors to be proved. Finally, an alternative method is developed for avoiding the state explosion in the case of asynchronous control circuits. This technique is based on the unfolding of Petri nets, and is used to check for hazards in a distributed mutual exclusion circuit.

Control of Discrete Event Systems

Abstract: Discrete Event Systems (DES) are a special type of dynamic systems The "state" of these systems changes only at discrete instants of time and the term "event" is used to represent the occurrence of discontinuous changes (at possibly unknown intervals) Different Discrete Event Systems models are currently used for specification, verification, synthesis as well as for analysis and evaluation of different qualitative and quantitative properties of existing physical systems The main focus of this paper is the presentation of the automata and formal language model for DES introduced by Raniadge and Wonham in 1985 This model is suitable for the examination of some important control theoretic issues, such as controllability and observability from the qualitative point of view, and provides a good basis for modular synthesis of controllers We will also discuss an Extended State Machine and Real-Time Temporal Logic model introduced by Ostroff and Wonham in [OW87] It incorporates an explicit notion of time and means for specification and verification of discrete event systems using a temporal logic approach An attempt is made to compare this model of DES with other ones Comments University of Pennsylvania Department of Computer and Information Science Technical Report No MSCIS-92-35 This technical report is available at ScholarlyCommons: http://repositoryupennedu/cis_reports/523 Control of Discrete Event Systems MS-CIS-92-35 GRASP LAB 313

Estimation of average switching activity in combinational and sequential circuits

Abstract: The authors address the problem of estimating the average power dissipated in VLSI combinational and sequential circuits, under random input sequences. Switching activity is strongly affected by gate delays and for this reason a general delay model is used in estimating switching activity. The method takes into account correlation caused at internal gates in the circuit due to reconvergence of input signals. In sequential circuits, the input sequence applied to the combinational portion of the circuit is highly correlated because some of the inputs to the combinational logic are flip-flop outputs representing the state of the circuit. Methods are presented to probabilistically estimate switching activity in sequential circuits. These methods automatically compute the switching rates and correlations between flip-flop outputs. >

What Good Are Digital Clocks

Abstract: Real-time systems operate in “real,” continuous time and state changes may occur at any real-numbered time point. Yet many verification methods are based on the assumption that states are observed at integer time points only. What can we conclude if a real-time system has been shown “correct” for integral observations?

Symbolic model checking for real-time systems

Abstract: Finite-state programs over real-numbered time in a guarded-command language with real-valued clocks are described. Model checking answers the question of which states of a real-time program satisfy a branching-time specification. An algorithm that computes this set of states symbolically as a fixpoint of a functional on state predicates, without constructing the state space, is given. >

Bar code lottery ticket handling system

Abstract: A point of sale system involving a series of check stands with POS cash registers and bar code scanners includes a lottery ticket issuing and redemption system. A number pick stand in the store, apart from the checkout stands, enables the customer to choose numbers. Pick slips can be generated by the customer at this stand, and bear a bar coded transaction number which can be communicated to a lottery device at each check stand. The pick slip is readable at the check stand bar code reader along with a series of store-inventory items. The customer is automatically charged for the lottery ticket, and the ticket is printed at the check stand. At the time the ticket is issued, the lottery transaction is recorded via modem to the central lottery computer of the state or other controlling agency. In another embodiment the number pick stand may encode the actual picked numbers on the pick slip, in an extended field bar code. The system of the invention enables lottery ticket transactions to be smoothly and efficiently handled at each check stand of a supermarket without in substantially the same manner grocery items are handled and without burdensome and expensive duplication of lottery equipment.

Learning and Instruction with Computer Simulations: Learning Processes Involved

Abstract: Nowadays prevalent learning theories state that in the study process the learner is actively involved in constructing and reconstructing his/her knowledge base. This conclusion is reflected in modern approaches to teaching that have abandoned viewing the learner as an ‘empty box’ into which knowledge could be poured, and stress the active role of the learner and the importance of his/her foreknowledge. Some forms of Computer Assisted Instruction are well suited for this teaching approach. The use of hypertext-like systems, in which learners are encouraged to explore a domain, is such an example. A second example of CAI that elicits exploratory behaviour is simulation-based learning.

Method and system for instructing a user of a computer system how to perform application program tasks

Abstract: A method and computer system for coaching a user how to perform application program tasks is provided. The user activates the coaching program of the present invention while an application program is running on the computer system. If the user needs such assistance, the coaching program helps the user determine the next task the user wishes to perform in the application program. The coaching program then determines if the application program is in the correct state for performance of the next task. If the application program is not in the correct state, the coaching program guides the user through performing essential preliminary tasks that place the application program in the correct state for performance of the next task. The computer system simultaneously displays on the display screen output, such as application program instructions, generated by the coaching program and a user interface display generated by the application program. Output generated by the coaching program always overlays the user interface display in such a way that it does not block the working portion of the user interface display and it does not interrupt the operation of the application program. The user performs the next task in the application program by interacting with the working portion of the user interface display, while the computer system continues to display the output generated by the coaching program. This enables the user to read instructions displayed on the display screen on how to perform the next task during performance of the next task.

Chemical implementation of finite-state machines

Abstract: With methods developed in a prior article on the chemical kinetic implementation of a McCulloch-Pitts neuron, connections among neurons, logic gates, and a clocking mechanism, we construct examples of clocked finite-state machines. These machines include a binary decoder, a binary adder, and a stack memory. An example of the operation of the binary adder is given, and the chemical concentrations corresponding to the state of each chemical neuron are followed in time. Using these methods, we can, in principle, construct a universal Turing machine, and these chemical networks inherit the halting problem

Computer language structure for process control applications and method of translating same into program code to operate the computer

Abstract: A language structure and translator specifically adapted for use in constructing computer programs for controlling chemical and physical processing. The translator converts to compilable code programs written as statements expressing control intentions or results. Each textual function and statement is expressed as a data structure which expresses the function, as configured, and the state and values most recently calculated for the relevant variables. Provision is made for treating the program structure (i.e., control connections, program order and components, etc.) as a part of the dynamic state of the application. Graphical symbols, or icons, are employed to draw the eye to critical features in the control program and to lead the eye through critical interrelationships among the several commands of a complicated control system. At the same time, the translator treats the keystrokes generating these icons as statements (i.e., commands) which define the relationships among other associated program statements (which are usually textual commands), to control the order in which the operations represented by those statements are executed.

Boundary scan architecture extension

Abstract: A method and apparatus provides improved modes of operation of a standard test bus based on a standard boundary scan architecture which minimizes the number of bits required to be serially scanned into the controllers of the various devices connected to the bus by temporarily disabling scan paths not required to be utilized. Means for continuously verifying the inoperative state of test logic and for diagnosing test logic faults are also described.

Nonvolatile semiconductor memory device and an optimizing programming method thereof

Abstract: A nonvolatile semiconductor memory device particularly relates to an EEPROM having NAND-structured cells, and an optimizing programming method thereof. The device includes a memory cell array arranged as matrix having NAND cells formed by a plurality of serially-connected memory cells each of which is formed by stacking a charge storage layer and a control gate on a semiconductor substrate, and enables electrical erasing by the mutual exchange of a charge between the charge storage layer and the substrate, a data latch circuit, a high voltage supply circuit, a current source circuit, a program checking circuit, and a program status detecting circuit. The programming state is optimized while being unaffected by the variance of process parameters, over-programming is prevented by the use of a verifying potential, and the performance of the chip is enhanced by automatically optimizing the programming with a chip's internal verification function. External control is not required, which enhances performance of the overall system. Also, a page buffer of an existing flash memory having the page mode function is employed, which is applicable to the currently used products.

Synthesis of 3D asynchronous state machines

Abstract: A synthesis procedure for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple-input-change fundamental mode operation, is described. This implementation of burst-mode state machines uses standard combinational logic, generates low-latency outputs and guarantees freedom from hazards at the gate level. It requires no locally synthesized clock and no storage elements. In addition, primary outputs as well as additional state variables are used as feedback variables. The state assignment technique is based on the construction of a three-dimensional next-state table. >

Real-time statistical process monitoring system

Abstract: A system for monitoring a multiparameter manufacturing process by examining on a real-time basis a stream of data units, each data unit including a numerical characteristic indicative of a current state of one of the parameters of that manufacturing process and a tag identifying the parameter. The system employs an entity-relational database to group and evaluate all data units using statistical evaluation criteria, and to identify and generate signals relating to particular testpoints in the manufacturing process so that an indication of the significance of the statistical pattern and the manufacturing process parameter involved are given in such terms as to permit human evaluation of and, if necessary, manual or automatic intervention in the manufacturing process.

FPGA architecture including direct logic function circuit to I/O interconnections

Abstract: A user-programmable FPGA architecture includes a plurality of logic function circuits having inputs and outputs disposed on an integrated circuit. A plurality of input/output (I/O) modules are also disposed on the integrated circuit and communicate with I/O pads on the integrated circuit. The I/O modules each include: (1) an input buffer having an input connected to an I/O pad on the integrated circuit and an output connected to an output node, and (2) an output buffer having an input connected to an input node, an output connected to the I/O pad, and a control input connected to a control node for placing the output buffer into a high impedance state. A general interconnect structure disposed on the integrated circuit includes a plurality of interconnect conductors which may be connected to one another, to the inputs and outputs of the logic function circuits, and to the I/O modules by programming user-programmable interconnect elements. Direct interconnections are made between the inputs of selected ones of the logic function circuits and the output nodes of selected ones of the I/O modules. Direct interconnections are made between the outputs of selected ones of the logic function circuits and the input nodes of selected ones of the I/O modules. Direct interconnections are made between the outputs of selected ones of the logic function circuits and the control nodes of selected ones of the I/O modules.

Method and apparatus for increasing the speed of the detecting of computer viruses

Abstract: A method and apparatus for increasing the speed at which a computer can scan files for computer viruses examines the initial state information of each file and stores this state information in a cache. Since viruses generally add themselves to preexisting files, they generally change the lengths or other characteristics of the files. During a scan, current state information is gathered regarding the length and/or other characteristics of the current state of the file and this information is compared to the length and characteristics from the initial state of the file. If the initial state information is different than the current state information then the files are scanned for certain subsets of viruses which affect files in a manner which is determined by the differences in such initial and current state information.

Theory of CMOS Digital Circuits and Circuit Failures

Abstract: CMOS chips are becoming increasingly important in computer circuitry. They have been widely used during the past decade, and they will continue to grow in popularity in those application areas that demand high performance. Challenging the prevailing opinion that circuit simulation can reveal all problems in CMOS circuits, Masakazu Shoji maintains that simulation cannot completely remove the often costly errors that occur in circuit design. To address the failure modes of these circuits more fully, he presents a new approach to CMOS circuit design based on his systematizing of circuit design error and his unique theory of CMOS digital circuit operation. In analyzing CMOS digital circuits, the author focuses not on effects originating from the characteristics of the device (MOSFET) but on those arising from their connection. This emphasis allows him to formulate a powerful but ultimately simple theory explaining the effects of connectivity by using a concept of the states of the circuits, called microstates. Shoji introduces microstate sequence diagrams that describe the state changes (or the circuit connectivity changes), and he uses his microstate theory to analyze many of the conventional CMOS digital circuits. These analyses are practically all in closed-form, and they provide easy physical interpretation of the circuit's working mechanisms, the parametric dependence of performance, and the circuit's failure modes. Originally published in 1992. The Princeton Legacy Library uses the latest print-on-demand technology to again make available previously out-of-print books from the distinguished backlist of Princeton University Press. These editions preserve the original texts of these important books while presenting them in durable paperback and hardcover editions. The goal of the Princeton Legacy Library is to vastly increase access to the rich scholarly heritage found in the thousands of books published by Princeton University Press since its founding in 1905.

Algorithms for the Container Loading Problem

Abstract: In this paper we consider the three-dimensional problem of optimal packing of a container with rectangular pieces. We propose an approximation algorithm based on the “forward state strategy” of dynamic programming. A suitable description of packings is developed for the implementation of the approximation algorithm, and some computational experience is reported.

ARCHON: theory and practice

Abstract: This paper describes the state of the ARCHON project at its halfway stage. It outlines why a Distributed AI approach is appropriate for large industrial applications, the benefits which accrue and highlights those domain characteristics which have had significant bearing on the design process. The ARCHON functional architecture is described and a clear mapping with the design forces is made. The problem of constructing a general architecture which is sufficiently powerful for real-size applications is raised and two mechanisms used within ARCHON for achieving this objective are identified. The first mechanism is to combine generic, declarative knowledge related to cooperation and control with situated action formalisms which are tailored to the particular application. The second approach is to provide general structures which can be instantiated with domain specific information.

System and method for supporting context switching within a multiprocessor system having functional blocks that generate state programs with coded register load instructions

Abstract: A context switching system for saving, restoring or swapping tasks, and is adapted for use in a multitasking processor coupled to an external or system memory. The processor includes one or more functional blocks to perform the tasks. The functional blocks comprise registers that store state data that, at a particular instant, represents the context of the system. The system comprises a controller that receives a save or switch command and generates a context save instruction in response thereto. The controller is configured to pass the context save instruction to the functional blocks. The functional blocks generate a state program. The state program comprises one or more register load instructions and the state data representing the context of the system so that context can be restored at a later time. The state program is stored in an external or system memory. Saving context as state programs permits the system to quickly switch from one context to another without losing important information.

History-less checking of dynamic integrity constraints

Abstract: An efficient implementation method is described for dynamic integrity constraints formulated in past temporal logic. Although the constraints can refer to past states of the database, their checking does not require that the entire database history be stored. Instead, every database state is extended with auxiliary relations that contain the historical information necessary for checking constraints. Auxiliary relations can be implemented as materialized relational views. The author analyzes the computational cost of the method and outlines how it can be implemented by using existing database technology. Related work on dynamic integrity constraints is surveyed. >

Fast sense amplifier

Abstract: An integrated circuit sense amplifier includes a pair of complementary inputs for receiving a pair of complementary data signals which are input to a CMOS flip-flop having its output nodes connected to a logic low through a first transistor and its high side connected to a logic high through a second transistor. The first transistor is on when data signals are not being sensed, holding the nodes in a no-current, logic low state. The first transistor turns off and the second transistor turns on just prior to the arrival of a signal, precharging the nodes to an intermediate voltage, permitting the flip-flop to latch more quickly to a full-logic output when the signal arrives. A preamp may be interposed between the complementary inputs and the latch. The preamp inputs and outputs are precharged to voltage levels near or between their anticipated final levels, so that they reach their final levels quickly when the data signal arrives. The flip-flop output nodes may be connected to a tristate output circuit, which is also precharged to an intermediate level, enabling it to reach its full output more quickly.

Apparatus for storing "Don't Care" in a content addressable memory cell

Abstract: A content addressable memory cell is able to store a state representing "Don't Care", by storing two bits of data The "Don't Care" state is indicated by storing two identical bits corresponding to a predetermined value, so that the cell indicates a match regardless of the match data When the cell is not in the "Don't Care" state, two complementary bits are stored, so that the cell indicates a match only when the match data matches the state of the first of the two bits

Sharing of bus access among multiple state machines with minimal wait time and prioritization of like cycle types

Abstract: Conflicting users of a shared resource are controlled by respective state machines having cross-coupled busy signals permitting each user to proceed with exclusive use of the shared resource when the other users are finished using the resource. Priority logic responsive to service requests issues grant signals to the state machines so that the state machines do not permit their respective users to begin simultaneously exclusive use of the resource. Preferably, each state machine also receives the requests for service of its respective user. Each state machine, for example, has an idle state, a first state reached from the idle state in response to a service request; a second state reached from the first state in response to a grant signal; and a third state reached from the second state, unless the busy signal of another state machine is asserted. Preferably, each state machine is responsive to a request having different preassigned priorities. The priority logic arbitrates among requests for services of different users, and each state machine arbitrates among the requests of different priorities for the service of its respective user. In a specific example, the users are DRAM memory banks that share a common data bus. The requests include read requests, write requests, and refresh requests. Read requests are given priority over write requests.

Computer system performance evaluation system and method

Abstract: A system for evaluating the performance of a computer system having a processor that passes through a plurality of processor states during operation and an associated system memory includes an operating unit for receiving a request to monitor specific process states from a user. Firmware causes the processor to enter the desired processor state requested by the user. The hardware identifies the occurrence of the desired processor state. Information relating to the occurrence of the desired process state is accumulated the memory. The accumulated information is read from memory and a report is provided to the user.

Adaptive elevator security system

Abstract: An adaptive elevator security system has a security module (52) which uses data stored in a configuration data element (64) to update a security state data element (62) The security module (52) provides data from a raw car/hall call data element (56) to a filtered car/hall call data element (58) according to data stored in the security state data element (62)

Programming generic dynamic reconfigurations for distributed applications

Abstract: Gerel is a generic reconfiguration language, which can be used to describe and implement dynamically reconfigurable distributed applications. Gerel is based on a powerful object selection mechanism for dynamically selecting configuration objects according to their structural properties, which are expressed in Gerel's logic-based sublanguage Gerel-SL. Gerel also supports the definition of preconditions for programmed changes. These preconditions are evaluated at the beginning of the change's execution and ensure that the current configuration has the structural properties required by the change. All these features of Gerel are shown in the scenario of a patient monitoring system. Due to its object selection mechanism supporting full first order logic expressions, Gerel has more expressive power than other reconfiguration languages and supports the definition of generic changes. This means that programmed changes can also be designed to be robust to system evolution. By providing change preconditions, Gerel also gives a means for defining reliable programmed reconfigurations, which are only executed if the current configuration is in a state expected by the change and whose execution need not be coordinated among the corresponding invoking components. Therefore, Gerel's selection and precondition features support both re-usability of programmed changes for different domains and the strict separation of reconfiguration and application programming concerns. >

Mixed mode simulation method and simulator

Abstract: A mixed mode simulation method and apparatus are provided for highly accurately simulating the total characteristics of a digital analyzed circuit portion and an analog analyzed circuit portion, which are both subjected to mixed mode simulation, in consideration of the influence exerted on the analog analyzed circuit portion by a current consumed by the digital analyzed circuit portion. More particularly, a current value of an equivalent circuit for current calculation modeled for providing the analog analyzed circuit portion with a current generated due to an operating state of the digital analyzed circuit portion realized by logic simulation is determined in synchronism with the logic simulation, and the equivalent circuit for current calculation derived thereby is composed with the analog analyzed circuit portion, and this composite circuit is subjected to circuit simulation.