Showing papers on "State (computer science) published in 1993"

Hybrid Automata: An Algorithmic Approach to the Specification and Verification of Hybrid Systems

Abstract: We introduce the framework of hybrid automata as a model and specification language for hybrid systems. Hybrid automata can be viewed as a generalization of timed automata, in which the behavior of variables is governed in each state by a set of differential equations. We show that many of the examples considered in the workshop can be defined by hybrid automata. While the reachability problem is undecidable even for very restricted classes of hybrid automata, we present two semidecision procedures for verifying safety properties of piecewiselinear hybrid automata, in which all variables change at constant rates. The two procedures are based, respectively, on minimizing and computing fixpoints on generally infinite state spaces. We show that if the procedures terminate, then they give correct answers. We then demonstrate that for many of the typical workshop examples, the procedures do terminate and thus provide an automatic way for verifying their properties.

State of the art and perspectives

Abstract: Being asked to comment on the state of the art in machine translation and to predict its future bears a strong resemblance to being asked to read the Tarot. In neither case is very much solid objective data available on which to base an interpretation: in the case of the Tarot for obvious reasons, and in the case of machine translation mainly, perhaps, because the field is still relatively new, with no established or commonly accepted theoretical base, and one in which, although private industry has been able to construct and market application systems, the technology used is often carefully concealed or systematically misrepresented whilst the economic viability of the vendors frequently seems more like the raw material for a soap opera than information on which to base market predictions. In both cases, too, the wheel of fortune seems to play a major role. Launched into the limelight by a privately circulated memorandum 111, almost killed by government decree [2], partially restored to life through shifts in the weather [3], who would have predicted ten years ago when talk of machine translation still provoked a range of reactions between amused disbelief and downright hostility in the artificial intelligence community that DARPA would, in 1990, issue a call for proposals in the area, thus uncovering a strong but previously concealed interest in the topic in a surprisingly large number of research workers. In order, then, to avoid any semblance of a claim to specious authority, this response will be structured around five basic elements of one of the classic Tarot spreads. First we shall look at the seeker, the person questioning the cards for a way to respond to a specific problem. Then we shall look at what is beneath the seeker’s question the elements of the past which determine perception of the problem and of possible solutions. Next comes what is behind, the influences which have dominated recent history, but which may now be fading. Then we turn to the crown, the possible future which results from nothing going wrong, and finally we look at what is before, the immediate, inescapeable future which is already almost present.

Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system

Abstract: An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly

Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system

Abstract: A power conservation system in a computer system which includes a processing unit operating under control of an operating system. The computer system generates distinct call functions to the operating system where each call function is either in an active class or an idle class. The power conservation system has a plurality of states of operation including an ON state, a DOZE state, a SLEEP state and an OFF state. An activity monitor monitors the activity of the computer system and generating control signals for selecting one of the state of operation for the computer system. The activity monitor includes a storage for storing a call value for each distinct call function and activity threshold values for the various states of operation. The call values are weighted for the call functions whereby different call functions have a greater or lesser impact on the value of an activity level. The call value for each call function is retrieved when the call function is made to the operating system. The retrieved call values are sequentially accumulated to form an activity value which indicates the activity level of the computer system. A comparator compares the activity value with the threshold values and in response to the comparison generates a control signal to a power controller which selects the states of operation for the computer system, thereby regulating the power consumption of the computer system based on the activity of the computer system.

Circuit activity based logic synthesis for low power reliable operations

Abstract: A system developed to synthesize both finite state machines and combinational logic for low-power applications, called SYCLOP, is described. SYCLOP tries to minimize the transition density at the internal nodes of a circuit to minimize power dissipation during normal operation. As input signal probabilities and transition densities are considered during the synthesis process, a particular circuit can be synthesized in different ways for different applications that require different types of inputs. For the present state inputs to the combinational circuit of a state machine, simulation was used to determine the signal probabilities and transition densities. The algorithm is not limited by the number of bits used for state assignment. The multilevel optimization process extracts kernels so that there is a balance between area and power optimization. Results have been obtained for a wide range of MCNC benchmark examples. >

Method and apparatus for dynamic scheduling of instructions to ensure sequentially coherent data in a processor employing out-of-order execution

Abstract: A computer processor employing parallelism through pipelining and/or multiple functional units improved by Sequential Coherency Instruction Scheduling and/or Sequential Coherency Exception Handling. Sequential Coherency Instruction Scheduling establishes dependencies based on the sequential order of instructions, to execute those instructions in an order that may differ from that sequential order. Instructions are permitted to execute when all needed source operands will be available by the time required by the instruction and when all logically previous reads and writes of the destination will be accomplished before the time that the instruction will overwrite the destination. Sequential Coherency Exception Handling does not use checkpointing or in-order commit. Instead it permits out-of-order execution to actually update the permanent state of the machine out-of-order. It maintains and saves, when an exception is recognized, sequential flow information and completion information about the program execution. To resume the exception causing program after the exception is handled, the saved state is used to re-establish the program flow that was determined prior to the exception and to re-establish which instructions in that flow should not be executed, because they were completed before the exception occurred.

Computation of floating mode delay in combinational circuits: theory and algorithms

Abstract: Addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be unknown when a vector is applied at the inputs.) It is well known that using the length of the topologically longest path as an estimate of circuit delay may be pessimistic since this path may be false, i.e., it cannot propagate an event. Thus, the true delay corresponds to the length of the longest true path. This forces one to examine the conditions under which a path is true. The authors introduce the notion of static cosensitization of paths which leads to necessary and sufficient conditions for determining the truth or falsity of a single path, or a set of paths. The authors apply these results to develop a delay computation algorithm that has the unique feature that it is able to determine the truth or falsity of entire sets of paths simultaneously. This algorithm uses conventional stuck-at-fault testing techniques to arrive at a delay computation method that is both correct and computationally practical, even for particularly difficult circuits. >

Recursive finite state grammar

Abstract: A method and means for performing speech recognition are described. The method and means include multiple finite state grammars. The multiple finite state grammars include at least one global finite state grammar and at least one sub-finite state grammar. Each of the multiple finite state grammars includes multiple states and at least one transition arranged in a network. The transitions in the network are capable of including either terminals or non-terminals. Each of the terminals is associated with an acoustic model, while each of the non-terminals is associated with a call to one of the sub-finite state grammars. The present invention also includes a recognition engine which performs the recognition by traveling through the global finite state grammar. As terminals are encountered, the recognition engine matches the acoustic model of the terminal to the speech signals. As non-terminals are encountered, the recognition engine calls the sub-finite state grammar associated with the non-terminal and continues performing recognition by traversing the sub-finite state grammar. In traversing the sub-finite state grammar, the recognition engine matches the acoustic model to the speech signals to continue with the recognition. Upon traversing the sub-finite state grammar, the recognition engine returns to and continues traversing the global finite state grammar at the location of the call. In this manner, the speech signals are matched against the acoustic models in the global and sub-finite state grammars to generate textual output. I

An introduction to assertional reasoning for concurrent systems

Abstract: This is a tutorial introduction to assertional reasoning based on temporal logic. The objective is to provide a working familiarity with the technique. We use a simple system model and a simple proof system, and we keep to a minimum the treatment of issues such as soundness, completeness, compositionality, and abstraction. We model a concurrent system by a state transition system and fairness requirements. We reason about such systems using Hoare logic and a subset of linear-time temporal logic, specifically, invariant assertions and leads-to assertions. We apply the method to several examples.

Discovering dynamics: from inductive logic programming to machine discovery

Abstract: Machine discovery systems help humans to find natural laws from collections of experimentally collected data. Most of the laws found by existing machine discovery systems describe static situations, where a physical system has reached equilibrium. In this paper, we consider the problem of discovering laws that govern the behavior of dynamic systems, i.e., systems that change their state over time. Based on ideas from inductive logic programming and machine discovery, we present two systems for discovery of qualitative and quantitative laws from quantitative (numerical) descriptions of dynamic system behavior.

Computing the initial states of retimed circuits

Abstract: Retiming is an optimization technique for sequential circuits which consists in modifying the position of latches relative to blocks of combinational logic in order to minimize the maximum propagation delay between latches or to meet a given delay requirement while minimizing the number of latches If the initial state of the circuit is meaningful, one must compute an equivalent initial state for the retimed circuit after retiming The authors present a simple linear time algorithm to compute a correct initial state for a retimed circuit that can be used whenever the initial state of the original circuit satisfies a simple condition If this condition is not originally satisfied, it is shown how it can be automatically enforced by a logic synthesis tool with no need for user intervention >

Interface for translating an information message from one protocol to another

Abstract: A computer implemented interface for interfacing an equipment controller to an equipment manager each arranged to respond to a reproduced text messages according to a first and second protocol, respectively. The interface comprises a number of program modules (502-514) which each receive one or more inputs and produce an output dependent on whether defined conditions are met by the inputs. A number of the outputs of the program modules constitute inputs to other program modules therefore defining a network. A number of the program modules (502-508) are of the type which is responsive to a predefined text in a respective field of an input message to produce an output to a further program module which is responsive to a further predefined text in another field which is valid in a first protocol in the context of the predefined text. The network of program modules produces a series of outputs which represent the information content of the original input message. These outputs are then passed to a further series of modules which format a translation of the input message. The defined conditions of the program modules are modifiable and in particular are modifiable in a manner which is dependent on the state of part of the equipment management system thereby providing an inherent model of the network management system for use during parsing of an input message.

Power supply and method for use in a computer system to confirm a save operation of the computer system and to stop a supply of power to the computer system after confirmation

Abstract: A power supply for use in a computer system according to this invention has a one-chip microcomputer having a built-in A/D converter. The microcomputer, which has a communication function, performs a power off sequence for a computer system and a power off sequence for a hard disk drive built in the computer system, while communicating with the computer system. Further, the microcomputer detects the voltage and current of a chargeable battery, discriminates a low battery state, monitors a power switch, a hard disk drive switch and a reset switch, and monitors an input/output voltage.

Processing system for providing an in circuit emulator with processor internal state

Abstract: A processing system is configured for providing an external in circuit emulator with an internal execution state resulting from the execution by a first processor of an internal instruction stored in an internal instruction cache. The processing system includes a second processor which includes an internal instruction cache for also storing the internal instructions. The second processor is coupled to the first processor in a master/slave configuration to enable the second processor to duplicate the instruction executions of the first processor. The second processor includes an output for providing the internal execution state which is coupled to the in circuit emulator by an external address bus for providing the internal execution parameter to the in circuit emulator.

Field programmable gate array

Abstract: A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof

Debugging a computer program by simulating execution forwards and backwards in a main history log and alternative history logs

Abstract: A computer program is executed in a forward direction to create a current state of registers and memory for the program. During the forward execution of the program, the pre-existing values of registers and memory changed by each instruction are recorded in a main log. During interactive debugging, reverse execution is simulated by displaying the contents of specified registers or memory locations. For each specified register or memory location, the main log is searched in a forward direction beginning at a specified time in the past and continuing until a value is found, or until the end of the main log is reached and a value is taken from the current state for the computer program. After simulated execution in reverse, the user may specify a changed value for a specified register or memory location, and then forward instruction interpretation is begun using the changed value, without changing the current state. New values of registers and memory locations generated by forward interpretation are recorded in an alternative log. Values of registers and memory accessed by forward-interpreted instructions are fetched by first searching the alternative log in a reverse direction, and when a value is not found in the alternative log, the main log is searched in a forward direction as described above. Moreover, at any time during forward interpretation, the user may specify a changed value, the change is logged in an alternative log, and forward interpretation continues.

System and method for computer interface board identification by serially comparing identification address bits and asserting complementary logic patterns for each match

Abstract: A system and method for automatically identifying and configuring interface boards connected to a computer bus is disclosed. Each interface board contains a pair of interface ports that can be addressed by the system and a unique identification address. The interface boards are instructed to serially read the identification address and place a logic 10 in the two least significant bits of the data bus if the first data bit is a logic one. The serial read instruction is performed twice for each data bit in the identification address with a logic 01 data pattern placed on the data bus for the second serial read to assure that a floating data bus is not causing false readings. If no interface board responds to any particular read identification instruction, the system assigns a logic zero for that particular bit of the identification address. Any interface board not having a logic one for a particular first data bit in the identification automatically places itself in a disabled state if the first and second serial read instructions indicate that another interface board did have a logic one for that particular data bit of the identification address. By the time that the system has read all of the identification bits, one and only one interface board will have been identified and enabled. The system can read registers on the interface board to determine which resources are required for operation of that board and assigns parameters such as I/O address, interrupt line, and data channel line. The system enables the other previously disabled interface boards and repeats the identification instructions until all interface boards have been identified and configured.

Fuzzy logic and neural network applications in food science and technology

Abstract: Intelligent computer programs capable of state estimation and prediction into the future would be helpful as ‘software sensors’ when dealing with bioprocesses characterized by uncertainties and complexity. Fuzzy logic has been shown to be a valuable tool in dealing with vague and incomplete information, and in incorporating human expert knowledge into process models. Neural network programs capable of learning from past experience are useful when no exact mathematical information on the process under investigation is available. This paper discusses the state of the art of such novel tools of artificial intelligence, with examples demonstrating their potential in food-related applications.

Non-intrinsive method and system for recovering the state of a computer system and non-intrusive debugging method and system utilizing same

Abstract: A non-intrusive method and system for recovering the state of a computer system including a memory having first and second matched levels. The first level is connected to a target processor and the second level is connected to a checkpoint processor which is also connected to the target processor. In an example of the invention, a two phase, non-intrusive method and system for debugging parallel computer programs is provided. The program has checkpoint instructions therein. In the first phase the execution of the program is monitored non-intrusively from a bus connecting the target processor to the first level of memory. A sequence of relevant program instructions is stored in an event table. Upon encountering a checkpoint instruction, the target processor cues the checkpoint processor to initiate a non-intrusive checkpointing strategy utilizing the two-level memory with an E-bit scheme. In the second phase the information collected during the first phase is utilized to replay an identical execution of the program, in a simulated environment. A user, on encountering an error, can back up to a previous checkpoint and replay the program from that state of the computer system.

Distributed information processing system providing a resume function and resume method for the distributed information processing system

Abstract: A distributed information processing system which includes a server having a resume-request processor and clients having resume-request units or processor. An user at the client site operates a resume switch to save an operation state of the client in the server's magnetic disc, and resume it from the server's magnetic disc. The operation state includes contents of the main memory, contents of the display memory, values of the I/O registers for peripheral devices, and information about the file of the server being used by the application program run by the user. The user is able to use any client of the system in the same situation including a connection state between the file and the application program as before.

Method and apparatus for momentarily interrupting power to a microprocessor to clear a fault state

Abstract: A method and apparatus for providing notice of impending initialization prior to initializing a microprocessor to enable the microprocessor to store operating data prior to initialization and to use the stored operating data after initialization. The apparatus includes a notice device for supplying a notice signal to warn the microprocessor of an impending initialization and an interrupt device for supplying an interrupt signal to cause a switching device to momentarily interrupt electrical power to the microprocessor. The cycling of microprocessor power resets microprocessor operations that are sensitive to a power interruption. Upon restoration of microprocessor power, a reset device outputs a processor reset signal that forces the microprocessor to reboot and execute an initialization program. The processor reset signal also synchronously resets the notice device and the interrupt device means to maintain the cycle of intentional initialization of the microprocessor. The microprocessor is programmed to recognize that an initialization of the processor is scheduled to occur and therefore operates to complete current program tasks and initiates the storage of a selected set of operating data. The microprocessor stores the operating data within a memory storage device that remains powered during the interruption of power to the microprocessor. In response to the initialization program, the microprocessor operates to detect whether the initialization of the microprocessor corrupted any of the selected operating data stored within the memory storage device. If the microprocessor finds that the stored operating data is valid, the microprocessor begins operations using the stored operating data.

System and method for producing input/output expansion for single chip microcomputers

Abstract: A microcomputer system providing high performance access to external Special Function Registers (SFRs), has an 8051 architecture microcontroller modified such that the instruction stream can be externally examined and decoded by an external expansion decoder. The instruction stream can be examined and decoded regardless of whether the microcontroller fetches instructions from an internal program memory or an external program memory. Every State 6, Phase 2, data on the internal bus of the modified microcontroller is transferred to the PORT2 pins and is available to the external expansion decoder. During reset the microcontroller latches the state of the EA pin to internally determine whether to operate in ROM or ROMless mode. Thereafter, EA operates as a bi-directional control pin that, as an output, signals whether the current bus cycle is an instruction fetch, and, as an input, signals whether the microcontroller shall read the data present on a certain set of I/O pins in order to complete an SFR read operation. The expansion decoder determines whether the current instruction is one which may operate on an SFR, and if so it further decodes the SFR address associated with the current instruction, and produces appropriate read and write control signals for accessing an external SFR. The expansion decoder may contain either a fixed or programmable table of valid external SFR addresses. External SFR addresses represent peripheral functions, increased data memory or both. The system reduces the number of cycles required to access an external device in an 8051 architecture system by providing access to external devices as if they were architecturally internal devices.

Clock-synchronous semiconductor memory device and method for accessing the device

Abstract: A method for accessing a clock-synchronous semiconductor memory device including memory cells arranged in matrix. The cells are divided into at least two blocks, access to the cells in these blocks is designated from address data provided from an external device, and access to the memory cell is executed synchronously with an externally-supplied clock signal, which comprises setting the other blocks in an access preparation state or in an access operation standby state while one block is in an access operating state, setting a certain block in the access operating state via the access preparation state when the certain block is designated for the access operation by the address data and if the certain block is in the access operating state, and setting a certain block in the access operating state immediately when the certain block is designated for the access operation by the address data and if the certain block is in the access preparation state or in the access operation standby state. In the device, the designation of the cell in the block to be accessed is set using address data designating a block externally-provided from outside of the device.

Computer program analyzer for adapting computer programs to different architectures

Abstract: An extended mode analyzer (EMA) processes source code modules, detects suspicious instruction patterns and produces recommendations for code modification. The EMA applies knowledge based technology to the problem of massive source code conversion. The knowledge base component within the EMA models any given source code module using a hierarchical class/attribute structure. All source lines occurring in a given module are partitioned into homogenous classes characterized by function or instruction type. Higher level programming concepts are abstracted from lower level implementation details by drawing correspondences between class members which constitute instruction sequences related by common elements. When inferencing begins, the existence of class members meeting certain criteria trigger events which change the state of the world as seen by the knowledge base, in turn triggering other state changing events and so on until a state of equilibrium is achieved. The end result of this process is the body of recommendations produced by EMA for source code conversion.

Towards a Provably Correct Hardware Implementation of Occam

Abstract: This paper shows how to compile a program written in a subset of occam into a normal form suitable for further processing into a netlist of components which may be loaded into a Field-Programmable Gate Array (FPGA). A simple state-machine model is adopted for specifying the behaviour of a synchronous circuit where the observable includes the state of the control path and the data path of the circuit. We identify the behaviour of a circuit with a program consisting of a very restricted subset of occam. Algebraic laws are used to facilitate the transformation from a program into a normal form. The compiling specification is presented as a set of theorems that must be proved correct with respect to these laws. A rapid prototype compiler in the form of a logic program may be implemented from these theorems.

Method of recording, playback and re-execution of application program call sequences and import and export of data in a digital computer system

Abstract: An operator of a digital computer system enters application call commands to execute a series of application programs. The execution of the application programs is affected by application operational commands, and involves the import and export of data among the application programs. The data are imported and exported through objects such as files. The computer system includes a core executive program that records a script of the application call commands. The application programs each include a client executive routine that records the application program's operational commands together with import and export information, and transmits the operational commands and the import and export information to the core executive program before termination of the application program. The core executive program integrates the operational commands into the script, and displays a graphical picture of the state of the computer system. The graphical picture includes application icons indicating the application programs that have been called, and object icons indicating the transfer of data among the application programs. Moreover, the core executive program is responsive to the operator to replay the script by calling the application programs for execution according to the operational commands in the script.

Automatic design verification

Abstract: Methods and apparatus for formal verification. In one embodiment, values within a full model for formal verification are parameterized so that the parameters may be defined in order to perform verification on a reduced model. The number of states may then be reduced to allow formal verification on portions of a logic model of complex circuits such as microprocessors using present formal verification techniques. Preprocessor directives are used for multiple and conditional hardware description language generation for representation of a logic model of an integrated circuit, such as a microprocessor. Signals may also be freed from their associated circuitry, and placed into a non-deterministic state. Signals may also be set to a deterministic, designer-specified value. Associated circuitry may then be removed from the logic model for verification of a reduced model. Circuitry specified as "blocks" may also be entirely removed from the model, and all associated circuitry used as inputs to the removed blocks and associated signals may also be removed. Any of these are performed using pre-processor directives. A reduced logic model of a full logic model may then be generated which is used for formal verification.

Boundary-scan testable system and method

Abstract: A system (10) includes any number of Boundary-Scan integrated circuits (28), a common bus (14), and a Boundary-Scan master (22). The integrated circuits (28) include mode selection logic (58) that isolates pins (30, 32) from core logic (34) during Capture-DR, Update-DR, Run-Test/Idle, and Select-DR-Scan states (66, 88, 62, 64) when a system action instruction is active so that a system action may be asserted. During all other states, including a Shift-DR state (82), the pins (30, 32) remain coupled to the core logic (34). The Boundary-Scan master (22) includes an arbitration interface (112). The arbitration interface (112) requests control of the common bus (14) prior to the time when the integrated circuits (28) assert a system action. The Boundary-Scan master arbitration interface (112) then releases control of the common bus after system action by the integrated circuits (28) is completed.

Power saving control system for computer system

Abstract: A power saving control system for a computer system including a CPU, is provided with a mode selecting circuit for selectively operating the CPU in a first mode with relatively high performance and high power consumption and a second mode with relatively low performance and low power consumption, a repeated access detecting circuit for monitoring addresses accessed by the CPU over a given period in order to detect a predetermined operational state of the CPU, in which only specific address group is repeatedly accessed, a control circuit associated with the first means for normally operating the first means in the first mode and responsive to the second means detecting the predetermined operational state, for operating the first means in the second mode as long as the predetermined operational state is maintained, and a state display for generating an indication perceptible by an operator of the computer system indicating current operational mode of the CPU.

Apparatus and method for speculatively executing instructions in a computer system

Abstract: A compiler groups instructions into sets. The sets of instructions are related by data and control dependencies which are unresolvable by the compiler. Sets of instructions having unresolved dependencies are executed in a speculative state of the computer system under the assumption that an exception condition will not occur. However, if an exception condition does occur while executing a set of instructions in the speculative state, that exception condition is detected and the set of instructions is re-executed in a real state of the computer system to resolve the exception condition.