Showing papers on "State (computer science) published in 1995"

Libckpt: transparent checkpointing under Unix

Abstract: Checkpointing is a simple technique for rollback recovery: the state of an executing program is periodically saved to a disk file from which it can be recovered after a failure. While recent research has developed a collection of powerful techniques for minimizing the overhead of writing checkpoint files, checkpointing remains unavailable to most application developers. In this paper we describe libckpt, a portable checkpointing tool for Unix that implements all applicable performance optimizations which are reported in the literature. While libckpt can be used in a mode which is almost totally transparent to the programmer, it also supports the incorporation of user directives into the creation of checkpoints. This user-directed checkpointing is an innovation which is unique to our work.

Performance Analysis of Embedded Software Using Implicit Path Enumeration

Abstract: Embedded computer systems are characterized by the presence of a processor running application specific software. A large number of these systems must satisfy real-time constraints. This paper examines the problem of determining the bound on the running time of a given program on a given processor. An important aspect of this problem is determining the extreme case program paths. The state of the art solution here relies on an explicit enumeration of program paths. This runs out of steam rather quickly since the number of feasible program paths is typically exponential in the size of the program. We present a solution for this problem, which considers all paths implicitly by using integer linear programming. This solution is implemented in the program cinderella which currently targets a popular embedded processor - the Intel i960. The preliminary results of using this tool are presented here.

Semiconductor disk system having a plurality of flash memories

Abstract: A NAND bus interface independently receives 16 ready/busy signals from 16 flash EEPROM chips and thereby separately manages the operating states of these flash EEPROMs. Once a flash EEPROM as a write access target is set in a ready state, a write access to this write access target flash EEPROM is started without waiting for completion of the operations of all the flash EEPROMs. Each flash EEPROM is of a command control type capable of automatically executing a write operation. This allows parallel processing of the flash EEPROMs, i.e., a write access to a given EEPROM can be performed while a data write to another flash EEPROM is being executed. An ECC calculating circuit calculates a data string transferred in units of 256 bytes from a data buffer by a processor, and generates an ECC corresponding to that data string. The 256-byte data string is added with the generated ECC and transferred to a data register of a flash EEPROM. Even if abnormal cells are produced at the same bit position in a plurality of pages of a flash EEPROM, only one abnormal cell is contained in a data string as an object of the ECC calculation. This makes it possible to perform error detection and correction by a common simple ECC calculation without using any complicated ECC arithmetic expression with a high data recovery capability.

Map-matching navigation system

Abstract: A map matching navigation system for monitoring vehicle state characteristics including the location of a vehicle on a map route. The map matching navigation system may operate in a fixed mode wherein the map route is inputted by a user or a flexible mode wherein the map matching navigation system determines the map route from a plurality of measured points which correspond to the location of the vehicle. The map matching navigation system additionally updates the location of the vehicle at a plurality of positions on the map route wherein the vehicle location is known with an increased level of confidence.

Grafcet: a powerful tool for specification of logic controllers

Abstract: Basically, a logic controller is a discrete-event system whose purpose is to control the behavior of a process which is itself (seen by the controller as) a discrete-event system, taking into account the state of this process and other information coming from an operator or from other systems. In the early 1970s, the need to describe increasingly complex logic controllers was becoming evident, since the programmable logic controllers (PLC) were becoming more powerful and more extensively used. This paper shows how Grafcet can be used for this purpose. Grafcet is a tool, drawing its inspiration from Petri nets (a general purpose mathematical tool allowing various discrete-event systems to be described), whose aim is the specification of logic controllers. It is the basis of the sequential function chart (SFC), an International Standard in 1987. This paper, introductory in nature, explains the Grafcet model using the classical-state table model and presents a method for interpreting grafcets. >

State in Haskell

Abstract: Some algorithms make critical internal use of updatable state, even though their external specification is purely functional. Based on earlier work on monads, we present a way of securely encapsulating stateful computations that manipulate multiple, named, mutable objects, in the context of a non-strict, purely-functional language. The security of the encapsulation is assured by the type system, using parametricity. The same framework is also used to handle input/output operations (state changes on the external world) and calls to C.

Microcontroller with security logic circuit which prevents reading of internal memory by external program

Abstract: A microcontroller (20) provides security for internal instructions and data while allowing instruction fetches to external, off-chip memory connected to an expansion bus (30). A central processing unit (CPU) (21) provides a load instruction register signal to indicate when an access is an instruction fetch. When the load instruction register signal is active while the address is within the range of an on-chip nonvolatile memory (25), a security logic circuit (40) is reset to a first state. In this first state, the security logic circuit (40) also allows non-instruction fetches from the nonvolatile memory (25). However when the load instruction register signal is active while the address is not within the range of the nonvolatile memory (25), the security logic circuit (40) is set to a second state. While in this second state, the security logic circuit (40) disables attempted accesses to the nonvolatile memory (25). The security feature is selectively enabled or disabled as determined by a configuration register (23).

A method for the design of fault detection experiments

Abstract: A methodical procedure for organization of fault detection experiments for synchronous sequential machines possessing distinguishing sequences (DS) is given. The organization is based on the transition checking approach. The checking experiment is considered in three concatenative parts: 1) the initial sequence which brings the machine under test into a specific state, 2) the α-sequence to recognize all the states and to establish the information about the next states under the input DS, and 3) the β-sequence to check all the individual transitions in the state table.

Power estimation methods for sequential logic circuits

Abstract: Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2/sup N/ where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies. >

Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells

Abstract: A method and circuit programs and automatically verifies the programming of selected EEPROM cells without alternating between programming and reading modes like prior art methods and circuitry. The circuitry includes a programming circuit and a bit line voltage regulation circuit. The programming circuit further includes a novel sense amplifier which unlike prior art sense amplifiers, is operable during both cell reading and programming modes. Included in the sense amplifier are two current providing circuits. A first circuit provides current to a selected EEPROM cell which is sufficient for reading the programmed state of the cell, and a second circuit which automatically provides additional current when required, for programming the cell. The sense amplifier detects when programming of a selected EEPROM cell has completed and causes programming of that cell to be terminated. The voltage regulation circuitry regulates the bit line voltage to the selected EEPROM cell's drain electrode. The programming circuitry, including the sense amplifier, and voltage regulation circuitry are shown to be shared between a plurality of bit lines through a bit line selection circuit.

Method and apparatus to emulate VLSI circuits within a logic simulator

Abstract: An emulation modeling apparatus (54) comprises a combination of a device under simulation (48) to be emulated and means for keeping the device under simulation (48) in a quiescent state at normal operating speeds and in a normal operating sequence so as to allow dual access to the emulation modeling apparatus (54) without loss of data or accuracy of functions One access is from a host simulation environment (26) while the other is from a model debug user interface (20) where internal architecturally visible registers and status are available to the user for greater debug control on the simulated subsystem within simulation environment (26) Specifically, any of a wide variety of physical VLSI circuits (48) to be modeled is kept in a quiescent state after power-on by a device control (50) It is then accessed through simulation means by simulated subsystem within a simulation environment (26), to change the architecturally visible internal state of the VLSI circuit (48) Control (50) brings VLSI circuit (48) out of the quiescent state and submits the requested simulated access After taking the response, control (50) returns VLSI circuit (48) again to its quiescent state so as to keep its internal state current The response is sent back to simulation environment (26) to update the simulated subsystem Independently, any user request for accessing the architecturally visible internal state of the circuit is gathered by model debug and user interface (20) Interface (20) enables control (50) to bring VLSI circuit (48) out of the quiescent state and to submit the user request access Subsequently, control (50) monitors the response and returns VLSI circuit (48) to its quiescent state so as to maintain the internal state of VLSI circuit (48) current Control (50) then sends the response back to user interface (20) VLSI circuit (48) thus is always kept ready and current for the next request, either from simulation environment (26) or from user interface (20) without having to reset it If any user defined breakpoint condition is met during the simulated accesses on the VLSI circuit (48), this information is forwarded by control (50) to simulation environment (26) for stopping the simulation and to user interface (20) to update the debug screen accordingly

An Integrated Formal Model of Scenarios Based on Statecharts

Abstract: State automata are an attractive means for formally representing scenarios. Scenarios describe how users interact with a system. However, the current approaches treat every scenario as a separate entity.

On-line try before you buy software distribution system

Abstract: A computer-based on-line system is provided for demonstrating software programs to a potential purchaser. The system receives from an on-line system a software program to be demonstrated, and maintains the software program in a locked state in order to prevent unauthorized duplication of the software program. The software program is enabled for execution upon selection by a user, and the user is allowed to subsequently operate or sample the software program. The system maintains the software program in the locked state during the sampling in order to prevent unauthorized duplication of the software program. The sampling of the software program is selectively disabled, such as when the user completes the sampling or if the system detects that the user is attempting to copy the sampled application.

Employee time entry and accounting system

Abstract: A time entry and accounting system permitting employees to clock in and clock out from work at computerized time clocks located adjacent to their workstations using an individually encoded identification card. The time clock is configured to have a normally closed state and an opened state and to move between states in response to a supervisor scanning his identification card. The computerized time clocks are interactively linked to a central computer and, upon an employee clocking in or out, the central computer receives appropriate signals from the time clock, and stores information corresponding to these signals in memory. The information stored in the memory of the computer is subsequently used to develop accounting records and reports, to generate payroll data, and to send signals to the time clocks. The time clock further includes a display screen permitting the time clock to display messages in response to signals sent by the central computer and a plurality of buttons permitting an employee or supervisor to send additional information to the central computer.

Interpreter for performing remote testing of computer systems

Abstract: An interpretive language comprises instructions making up part of the first sequence of instructions (a test "script"). The first language comprises a first set of instructions, the first set of instructions causes a first computer system (a "host" in a preferred embodiment) to issue a series of commands to a second computer system (a "target") in order to cause the second computer system to emulate user activity on the second computer system. User activity includes emulating typing text and/or moving a mouse cursor position. The language further comprises a second set of instructions which cause the first computer system to issue a series of commands to the second computer system in order to cause the second computer system to respond to the first computer system with its state. This state includes user interface objects, and applications running in the target, etc. The language further comprises a third set of instructions, the third set of instructions causing the first computer system to issue a sequence of commands to the second computer system to respond in a predefined manner. These instructions indicate that the target computer system is to respond in within a given period of time, listen for further commands, etc. This is useful for repeatable and systematic testing of computer systems having a variety of hardware and software combinations for compatibility testing. Multitasking using "threads" for control of different targets using different test routines is also provided.

Multiple operations employing divided arithmetic logic unit and multiple flags register

Abstract: A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a combination of respective subsets of first and second multibit digital inputs. The arithmetic logic unit includes a status detector generating a single bit status signal indicative of said digital resultant signal of a corresponding section of the arithmetic logic unit. These single bit status signals are stored in predetermined locations within a multiple flags register. An options register stores an indication of the number of sections selected from a plurality of possible number of sections into which the arithmetic logic unit is divided. The arithmetic logic unit is further connected to the multiple flags register so that each section selects for output either corresponding bits of the first multibit digital input or the second multibit digital input dependent upon the digital state of a corresponding single status bit in the multiple flags register. This technique permits a variety of functions such as add with saturation, maximum, pixel transparency and color expansion.

Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions

Abstract: A pipeline control system for implementing a virtual architecture having a complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations These operations, each having an associated tag, are issued to the functional units Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory Operations are executed by the units in a manner that is generally independent of operation processing by the other units The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine Based on the termination information, the decoder logic retires normally terminated operations in order Thus, the functional units enable multiple operations to be executed in a speculative and out-of-order manner to fully utilize the resources of the processor

Access control mechanism controlling access to and logical purging of access register translation lookaside buffer (ALB) in a computer system

Abstract: An access control apparatus in a computer system for controlling access to an ALB. A host ALBID register and a guest ALBID register is provided for storing a host and a guest ALB identifier (ALBID) and a host and a guest ALBID validity indicator. Control State Software generates and stores the host and guest ALBIDs in the host and guest ALBID registers and marks valid the host and guest ALBID validity indicator whenever a host or guest mode is initiated or a logical purge is requested by a logical processor and for storing the host or guest ALBID stored in the host and guest ALBID registers when an ALB entry is made in the ALB by a logical processor. Access to an ALB entry by a logical processor is permitted when the logical processor is in the host mode if the ALBID in the ALB entry matches the host ALBID stored and the valid indicator is marked valid in the host ALBID register and when the logical processor is in the guest mode if the ALBID in the ALB entry matches the guest ALBID stored and the valid indicator is marked valid in the guest ALBID register. A host logical purge is accomplished by marking invalid the host and guest validity indicators in the host and guest ALBID registers. A guest Logical purge is accomplished by marking invalid the guest validity indicator in the guest ALBID register.

System management mode circuits, systems and methods

Abstract: An electronic system ( 100 ) includes a first integrated circuit (IC) ( 112 ) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ 3-5 ), and a logic circuit ( 1620, 1630 ) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate ( 2672 ) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate ( 2672 ) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit ( 110 ) has a system management interrupt (SMI#) output pin and SMI circuitry ( 2370 ) including a SMI register ( 2610 ) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC ( 110 ) further has a mask SMI register ( 2620 ) connected to the SMI register ( 2610 ) to select particular ones of the events sources for SMI response. A logic circuit ( 2634, 2638 ) is fed by the SMI register ( 2610 ) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Abstract: A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

A new approach for the verification of cache coherence protocols

Abstract: We introduce a cache protocol verification technique based on a symbolic state expansion procedure. A global Finite State Machine (FSM) model characterizing the protocol behavior is built and protocol verification becomes equivalent to finding whether or not the global FSM may enter erroneous states. In order to reduce the complexity of the state expansion process, all the caches in the same state are grouped into an equivalence class and the number of caches in the class is symbolically represented by a repetition constructor. This symbolic representation is partly justified by the symmetry and homogeneity of cache-based systems. However, the key idea behind the representation is to exploit a unique property of cache coherence protocols: the fact that protocol correctness is not dependent on the exact number of cached copies. Rather, symbolic states only need to keep track of whether the caches have 0, 1, or multiple copies. The resulting symbolic state expansion process only takes a few steps and verifies the protocol for any system size. Therefore, it is more efficient and reliable than current approaches. The verification procedure is first applied to the verification of five existing protocols under the assumption of atomic protocol transitions. A simple snooping protocol on a split-transaction shared bus is also verified to illustrate the extension of our approach to protocols with nonatomic transitions. >

Dynamic object visualization and browsing system

Abstract: A method to automatically monitor an object-oriented program, e.g., for debugging purposes, is characterized by the steps of determining a state of the digital data processor at selected points during execution of the program and, from that state, determining the status of objects created the program. The method also contemplates generating an animated graphical display reflecting the status of those selected objects, and their interrelationships, substantially concurrently with execution of the program.

Method and apparatus for reducing power consumption in a computer network without sacrificing performance

Abstract: A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independently initiating a transition into a power-conserving mode, i.e., a "sleep" state, while keeping its network interface "alive" and fully operational. Subsequently, each computer system can independently transition back into fully operational state, i.e., an "awake" state, when triggered by either a deterministic or an asynchronous event. As a result, the sleep states of the computer systems are transparent to the computer network. Deterministic events are events triggered internally by a computer system, e.g., an internal timer waking the computer system up at midnight to perform housekeeping chores such as daily tape backups. Conversely, the source of asynchronous events are external in nature and include input/output (I/O) activity. The illusion of the entire network being always fully operational is possible because the system controllers, the interconnects and network interfaces of each computer system remain fully operational while selected modules and peripheral devices are powered down. As a result, each computer system is able to rapidly awake from sleep state in response to stimuli by powering down selected modules thereby accomplishing power conservation without requiring a static shut down of the computer network, i.e., without the overall performance and response of the computer network.

Network hibernation system for suspending and resuming operation of computer system operable in network environment in event of power failure or period of inactivity

Abstract: A network hibernation system for use with a computer connected to a local area network. (LAN) which is capable of retaining both data from the computer and data from the network environment created in connection with the LAN in the event of a power failure and also in the event that the computer is idle for a predetermined time period. Upon the restoration of power, the states of the computer and network hibernation system are resumed to the point before the occurrence of the power failure or the idle period. The system includes a network interface for connecting the computer to the local area network; a power controller connected to a data bus, for generating a time-out signal when the computer is in a non-use state during operation of the computer; a power supply connected to the data bus, for generating a power interrupt detection signal upon abrupt termination of a main power source to provide back-up power to the computer system for backing data of the computer in a network environment, and for terminating the back-up power upon reception of a power interrupt signal; a supplemental memory for storing data of the computer in the network environment; a system controller connected to the data bus, for controlling data of the computer in the network environment to be stored in the supplemental memory, for generating the power interrupt signal after the data of the computer in the network environment are stored in the supplemental memory in response to either the time-out signal or the power interrupt detection signal to set the computer in a network hibernation state, and for recovering stored data and restoring the computer in the network environment when the main power source is re-supplied to the computer; and a main memory for storing network hibernation information for the system controller to determine whether the computer is in the network hibernation state.

Distributed state flags or other unordered information for embedded data blocks

Abstract: An embedded data block for storing machine readable information on a recording medium has a lattice-like sync frame which defines the outer boundaries of individual, fixed-size frame blocks. Flags, which are encoded by embedded data characters on the sync frame, indicate whether there are any special processing instructions (e.g., user-specific or application-specific instructions for customizing the processing of the data block) encoded within the frame blocks.

Computer process resource modelling method and apparatus

Abstract: An error detection mechanism for detecting programming errors in a computer program. A component of the computer program, e.g., a procedure or function of the computer program, is analyzed to determine the effect of the component on resources used by the computer program. A component is analyzed by traversing the computer instructions, i.e., statements, of the component and tracking the state of resources used by the components as affected by the statements of the component. Each resource has a prescribed behavior represented by a number of states and transition between states. Violations in the prescribed behavior of a resource resulting from an emulated execution of the statements of the component are detected and reported as programming errors. Resources used by two or more components are modelled by modelling externals of the components. The effect of execution of a component on externals and resources of the component is determined by traversing one or more possible control flow paths through the component and tracking the use of each external and resource by each statement of each control flow path. Once the effect of execution of a component on externals and resources of the component is determined, a model of the component is created and used to model externals and resources of other components which invoke the modelled component.

Self-launching encrypted try before you buy software distribution system

Abstract: A computer-based self-launching system associated with a software program is provided for demonstrating the software program to a potential purchaser of the program. The self-launching system is attached to a software program and includes the ability to launch itself when a user selects the software program. Upon launching itself, the system enables the software program for execution and allows the user to subsequently sample the software program. The system maintains the software program in a locked state during the sampling in order to prevent unauthorized duplication of the software program. The sampling of the software program is selectively disabled, such as when the user completes the sampling or if the system detects that the user is attempting to copy the sampled application.

System and method for saving state information in an interactive television system

Abstract: A computer-based system and method for saving and restoring states in an interactive television system. The system presents interactive programs to a user; each program includes one or more states. When a user leaves a state in an interactive program by selecting a second state, the system saves state information sufficient to restore the first state. When the user elects to return to the first state, the system retrieves the state information and uses it to restore the first state; if the first state is not in the same interactive program as the second state, the system terminates the second state's interactive program and launches the first state's interactive program.

Automated external defibrillator with lid activated self-test system

Abstract: An automated external defibrillator which automatically performs self-tests on a daily and weekly basis. Tested functions include the presence and interconnection of defibrillator electrodes, battery charge state and the operability of the high voltage circuit. Visual and audible indicators are actuated to alert an operator if faults are identified. A record of each self-test is stored in memory, and can be subsequently retrieved through a communications port.