Showing papers on "State (computer science) published in 1997"

GOLOG: A logic programming language for dynamic domains

Abstract: This paper proposes a new logic programming language called GOLOG whose interpreter automatically maintains an explicit representation of the dynamic world being modeled, on the basis of user supplied axioms about the preconditions and effects of actions and the initial state of the world. This allows programs to reason about the state of the world and consider the effects of various possible courses of action before committing to a particular behavior. The net effect is that programs may be written at a much higher level of abstraction than is usually possible. The language appears well suited for applications in high level control of robots and industrial processes, intelligent software agents, discrete event simulation, etc. It is based on a formal theory of action specified in an extended version of the situation calculus. A prototype implementation in Prolog has been developed.

System and method for performing flexible workflow process compensation in a distributed workflow management system

Abstract: A system and method for performing flexible workflow process execution in a distributed workflow management system is described. The distributed workflow management system is formed by a computer network comprising a plurality of computers. Each computer has a processor, memory and input/output facilities. A workflow process management system operates on one or more of the computers to control the computer network in executing the workflow process. The workflow process includes at least one sequence of multiple actions. A plurality of resources is coupled to respective ones of the computers to carry out the multiple actions. A plurality of state machines are stored as computer-operable code in at least one memory and include a plurality of states interconnected by arcs logically forming a directed graph. The workflow management system further includes logic for instantiating each action with one state and logic for executing the logical sequence of the action as state transitions in each state machine.

Process control system including automatic sensing and automatic configuration of devices

Abstract: A digital control system with a predetermined configuration automatically senses the connection to a network of a digital device that is not included in the predetermined configuration. The digital device is assigned temporary address information and placed in a temporary state, called a standby state, in which the digital device supplies information to the digital control system allowing a user to access the digital device including access of device information and configuration parameters. Using the device information and configuration parameters, a user selectively commissions the digital device by assigning a physical device tag, a device address, and a device identification, and installing a control strategy to the digital device, thereby placing the digital device in an operational state in communication with the digital control system. In the standby state, a user interrogates to determine the type of device that is attached, determines the role of the device in the context of the digital control system, assigns a physical device tag that assigns the determined role to the device, and verifies connection of the device to the network. Also in the standby state, the user initiates other applications applied to the device, including calibration of the device and configuring the device within the overall control scheme of the digital control system.

Sequential circuit test generation using dynamic state traversal

Abstract: This research was supported in part by the Semiconductor Research Corporation under contract SRC 96-DP-109, in part by ARPA under contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. A new method for state justification is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justification. State-transfer sequences may already be known that drive the circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justification sequences for the circuit in the presence of the target fault. This approach achieves extremely high fault coverages and thus outperforms previous deterministic and simulation-based techniques.

Copy protectable optical media device and methodology therefor

Abstract: A method and system is disclosed for purposefully modifying the accessibility of information encoded upon an optical medium (1150) for indicating a state or history of an item associated therewith. In one embodiment, the modifying of the optical medium (1150) includes a device (1170) for purposefully damaging the optical medium (1150) when the information is initially accessed so that upon subsequent attempts at accessing the information on the optical medium (1150), the previous access to the information can be detected by the access errors purposefully generated. Thus, the present invention provides an effective technique for limiting illegal duplication and/or use of, e.g., software, movies, and music on compact disks and digital versatile disks. Moreover, the present invention is also useful for verifying the authenticity of persons and/or financial transaction cards during financial transactions.

Power-management system for a computer

Abstract: A power management system for a personal computer comprises a power management processor, a switchable power supply and a keep alive power supply. The processor is powered by the keep alive power supply that continuously provides power. The computer is powered by a power supply that is switchable in response to a control signal. The processor preferably controls the switchable power supply. The processor is coupled to receive external device interrupts from a plurality of external devices that instruct the processor when to turn the switchable power supply on and off. The processor is also coupled to the computer through an interface. The power management system also includes a method for turning the computer on and off. A preferred method uses the processor to control the power provided to the computer. The preferred method also uses the processor to dictate whether the computer will to perform a long boot that brings the computer to an operational state, identifies the computer's configuration, and tests memory, or a short boot that brings the computer to an operational state in a much shorter time. A preferred method for turning the computer off includes the ability to exit a program being run by the computer, and saving a hardware state of the computer on a hard disk.

A method and apparatus for dynamically placing portions of a memory in a reduced power consumption state

Abstract: An apparatus and method for dynamically placing portions of a memory in a reduced power consumption state. Requests to access a memory that includes a plurality of rows of memory components are received. One or more of the plurality of rows of memory components are placed in a reduced power consumption state based on the requests while one or more other rows of the plurality of rows are accessed.

Object-oriented programmable controller

Abstract: A controller for one or more pieces of industrial equipment is configured to perform a series of control functions each organized into one or more procedures for performing particular machine actions. The progress of an action, or some parameter of the action-taking machine (which may or may not be associated with an action), is represented by one or more "states." A database associates entries corresponding to the items of an object (including the action(s) and the state(s)), and contains storage locations where the associated procedural instructions and/or data are to be found. The action can be independent of state information, or can instead be executed in a manner responsive to a sensed state. The controller may also include diagnostic capability, as well as accumulation and processing of performance data for subsequent analysis.

Fault tolerant computer system

Abstract: A fault tolerant computer system is disclosed which uses redundant voting at the hardware clock level to detect and to correct single event upsets (SEU) and other random failures. In one preferred embodiment, the computer (30) includes four or more commercial processing units (CPUs) (32) operating in strict "lock-step" and whose outputs (33, 37) to system memory (46) and system bus (12) are voted by a gate array (50) which may be implemented in a custom integrated circuit (34). A custom memory controller (18) interfaces to the system memory (46) and system bus (12). The data and address (35, 37) at each write to and read from memory (46) within the computer (30) are voted at each CPU clock cycle. A vote status and control circuit (38) "reads" the status of the vote and controls the state of the CPUs using hardware and software. The majority voted signals (35) are used by the agreeing CPUs 32 to continue processing operations without interruption. The system logic selects the best chance of recovering from a detected fault by resynchronizing all CPUs (32), powering down a faulty CPU or switching to a spare computer (30), resetting and re-booting the substituted CPUs (32).

Programmable cryptographic processing system and method

Abstract: A programmable crypto processing system (10) includes several processing resources (14, 16, 26) implemented on a single ULSI die. The processing system is both key and algorithm agile allowing for simultaneous execution of a variety of cryptographic programs through the use of background staging of the next program and context (key and state) during execution of a current program. The programmable crypto processing system includes a programmable crypto processor (17) for processing data units in accordance with a channel program, a crypto controller (11) for identifying a channel program, two interface processors (13, 15) for asynchronously receiving and transferring data units from and from an external host. Data units identify a particular channel program, and are processed in a selected processing engine in accordance the identified channel program. The interface processors are capable of full duplex operation and provide full physical data interface isolation for processing plain-text and cipher-text data.

Verification techniques for cache coherence protocols

Abstract: In this article we present a comprehensive survey of various approaches for the verification of cache coherence protocols based on state enumeration, (symbolic model checking, and symbolic state models. Since these techniques search the state space of the protocol exhaustively, the amount of memory required to manipulate that state information and the verification time grow very fast with the number of processors and the complexity of the protocol mechanisms. To be successful for systems of arbitrary complexity, a verification technique must solve this so-called state space explosion problem. The emphasis of our discussion is onthe underlying theory in each method of handling the state space exposion problem, and formulationg and checking the safety properties (e.g., data consistency) and the liveness properties (absence of deadlock and livelock). We compare the efficiency and discuss the limitations of each technique in terms of memory and computation time. Also, we discuss issues of generality, applicability, automaticity, and amenity for existing tools in each class of methods. No method is truly superior because each method has its own strengths and weaknesses. Finally, refinements that can further reduce the verification time and/or the memory requirement are also discussed.

State-based cache for antivirus software

Abstract: A computer-implemented method for executing a computer file in a CPU emulator (154) to detect a computer virus. The method includes simulating (302) the execution of a predetermined number of instructions of the computer file in the CPU emulator (154), suspending (303) the execution, constructing (304) a state record, temporarily storing (305) the state record in memory, comparing (306) the constructed state record to state records stored in a state cache (158), and indicating (308) that the file is virus free when the constructed state record matches one of the stored state records.

Method and apparatus for a computer power management function including selective sleep states

Abstract: The invention provides a power saving feature in a computer system such as a desktop computer using the Windows™ operating system. The computer system includes one or more "sleep" buttons which selectively reduce power consumption to subsystems based on the status of various consumer devices which share the subsystems with a computer function of the system. From the user's perspective, each sleep button acts as a power switch for the computer but not for devices associated with the computer. Each sleep button transitions the computer from its normal power-on state to one or more power saving states depending on which consumer devices are active.

Remote alert monitoring and trend analysis

Abstract: A monitoring system generates alerts indicating predefined conditions exist in a computer system Alerts are generated by comparing alert definitions to a host state representing the state of the hardware and software components of a computer system to determine if conditions defined in the alert definitions exist in the host state; and generating alerts accordingly The host state is a static tree structure including elements in a fixed hierarchical relationship, the elements being given value by associated tokens, the elements and associated tokens representing the hardware and software components of the computer system The alert definitions generate alerts according to the values of at least one token, at least one alert or a combination of various tokens and/or alerts The host state is created by providing a static tree structure representing a general computer system Component information indicating hardware and software components of the computer system is extracted from diagnostic data of the computer system The host state is generated according to the static tree structure and the component information

Information processing apparatus using finite state machine

Abstract: An information processing apparatus uses a triad-based state transition model which is implemented in a state machine for making rational determinations on the state of a system of interest and for controlling the same to an appropriate state. The triad-based state transition model is stored in a memory unit of the apparatus and made up of a first group of states for defining natural behavior of the system to be controlled irrespective of forced actions; a second group of states for defining forced actions for directing the behavior of the system to be controlled to a target; and a third group of state for defining target states to which the system to be controlled may proceed from the first group of states as a result of determining natural behavior of the system based on a first predetermined threshold value, and as a result of determining a change in the system behavior due to a forced action based on a second predetermined threshold value. The information processing apparatus has an interpreter unit for interpreting the state of the finite state transition machine for processing information on the system to be controlled and for controlling the system to be controlled based on a current state of the system to be controlled represented in the finite state transition machine.

Erase method for page mode multiple bits-per-cell flash EEPROM

Abstract: An improved erasing structure for performing a programming back operation and a concurrent verify operation subsequent to application of an erasing pulse in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and an erase verify reference cell array for generating an upper erased state threshold voltage level. A pre-charge circuit (36a) is used to pre-charge all the array bit lines to a predetermined potential prior to a programming back operation. A reference generator circuit (134) is used for generating a reference output voltage corresponding to a lower erased state threshold voltage level. A switching circuit (P1, N1) is used to selectively disconnect a program current source of approximately 5 νA from the selected certain ones of the columns of array bit lines containing the selected memory core cells which have been correctly programmed back. A sense logic circuit (26, 27) continuously compares a potential on one of the selected bit lines and the reference output voltage corresponding to the lower erase threshold voltage level.

Modem compatible method and apparatus for encrypting data that is transparent to software applications

Abstract: A method and apparatus for transmitting encoded data from one computer system to another using an AT command set compatible communication device is described. Data being sent from a communications application to the AT command set compatible communication device is monitored, and encryption is performed in response to detecting a connect message and a carrier detect signal received from the communication device and changing in response to said detection the state of an encryption application from a first state to a remote state and the data is encrypted using a stream encryption scheme before it is passed to the communication device. When a break sequence is detected or a carrier detect signal is deasserted, encryption is ceased thus having the encryption application automatically return to the first state.

Model Checking Coloured Petri Nets - Exploiting Strongly Connected Components

Abstract: In this paper we present a CTL-like logic which is interpreted over the state spaces of Coloured Petri Nets. The logic has been designed to express properties of both state and transition information. This is possible because the state spaces are labelled transition systems. We compare the expressiveness of our logic with CTL's. Then, we present a model checking algorithm which for efficiency reasons utilises strongly connected components and formula reduction rules. We present empirical results for non-trivial examples and compare the performance of our algorithm with that of Clarke, Emerson, and Sistla.

Synthesis of Finite State Machines: Logic Optimization

Abstract: Synthesis of Finite State Machines: Logic Optimization is the second in a set of two monographs devoted to the synthesis of Finite State Machines (FSMs). The first volume, Synthesis of Finite State Machines: Functional Optimization, addresses functional optimization, whereas this one addresses logic optimization. The result of functional optimization is a symbolic description of an FSM which represents a sequential function chosen from a collection of permissible candidates. Logic optimization is the body of techniques for converting a symbolic description of an FSM into a hardware implementation. The mapping of a given symbolic representation into a two-valued logic implementation is called state encoding (or state assignment) and it impacts heavily area, speed, testability and power consumption of the realized circuit. The first part of the book introduces the relevant background, presents results previously scattered in the literature on the computational complexity of encoding problems, and surveys in depth old and new approaches to encoding in logic synthesis. The second part of the book presents two main results about symbolic minimization; a new procedure to find minimal two-level symbolic covers, under face, dominance and disjunctive constraints, and a unified frame to check encodability of encoding constraints and find codes of minimum length that satisfy them. The third part of the book introduces generalized prime implicants (GPIs), which are the counterpart, in symbolic minimization of two-level logic, to prime implicants in two-valued two-level minimization. GPIs enable the design of an exact procedure for two-level symbolic minimization, based on a covering step which is complicated by the need to guarantee encodability of the final cover. A new efficient algorithm to verify encodability of a selected cover is presented. If a cover is not encodable, it is shown how to augment it minimally until an encodable superset of GPIs is determined. To handle encodability the authors have extended the frame to satisfy encoding constraints presented in the second part. The covering problems generated in the minimization of GPIs tend to be very large. Recently large covering problems have been attacked successfully by representing the covering table with binary decision diagrams (BDD). In the fourth part of the book the authors introduce such techniques and extend them to the case of the implicit minimization of GPIs, where the encodability and augmentation steps are also performed implicitly. Synthesis of Finite State Machines: Logic Optimization will be of interest to researchers and professional engineers who work in the area of computer-aided design of integrated circuits.

Method and apparatus for secure execution of software prior to a computer system being powered down or entering a low energy consumption mode

Abstract: A computer system that automatically and securely executes registered programs immediately prior to a transition to a reduced energy consumption state. A registrar table specifying registered programs and a secure modification detection value for each registered program are maintained in system management mode memory or other secure memory space in the computer system. A system management interrupt is generated following a request to remove power from the computer system or the occurrence of an event that triggers an energy saving mode. The system management interrupt handler routine then generates a current modification detection value for each registered program. The current modification detection values are compared with the secure modification detection values. Execution of a registered program is permitted if the values match. After all registered programs have been executed, the computer system automatically powers down or enters an energy saving mode. The computer system thereby allows secure and convenient execution of programs or commands that would typically interfere with normal computer use.

Formal verification of a TDMA protocol start-up mechanism

Abstract: This paper presents a formal verification of the start-up algorithm of the DACAPO protocol. The protocol uses TDMA (Time Division Multiple Access) bus arbitration. It was verified that an ensemble of four communicating stations becomes synchronized and operational within a bounded time from an arbitrary initial state. The system model included a clock drift corresponding to /spl plusmn/10/sup -3/. The protocol was modeled using a network of timed automata, and verification was performed using the symbolic model checker UPPAAL.

Semiconductor non-volatile latch device including embedded non-volatile elements

Abstract: A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a power up operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section. Means are provided for connecting the first circuit section and the second circuit section into a bistable configuration.

Method and circuitry for performing analog over-program and under-program detection for a multistate memory cell

Abstract: A method for detecting an under-programming or over-programming condition in a multistate memory cell. The method uses three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. Control circuitry is used which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell. This information is used by a controller to determine if a memory cell has been over-programmed, under-programmed, or properly programmed. If the cell has not been properly programred, then additional programming pulses are applied (in the case of under-programming) or an error flag is set and the programming algorithm is terminated (in the case of an over-programmed cell).

Debugging apparatus for debugging a program by changing hardware environments without changing program operation state

Abstract: A debugging apparatus is disclosed which verifies a program to be embedded into a target machine by running the program in an environment which is one or the target machine, an emulator, and a simulator. Each environment includes operation state information of the program and inputs and outputs the operation state information in a form unique to the environment. The debugging apparatus includes; target environment storing unit for storing an identification name of the target environment; receiving unit for receiving a command from an operator; instruction detecting unit for detecting a certain instruction in the command; specifying unit for, when the certain instruction is detected, specifying a target environment specified by the identification name as a source target environment and for specifying any of the rest of the environments as a destination target environment; reading unit for reading operation state information from the source target environment; converting unit for converting the operation state information into operation state information written in a form unique to the destination target environment; setting unit for setting the converted operation state information in the destination target environment; and operation resuming unit for resuming the operation of the program in the destination target environment.

Digital signal receiver

Abstract: Digital signal receiver for recording a plurality of program streams at the same time period with a single storage medium. The transport streams from the tuners T11 through T1n are converted into the program streams at the format conversion circuits F11 through F1n, then converted into the data forms corresponding to the data bus 5 in the data bus interfaces IF11 through IF1n, so as to output them to the data bus 5. Therefore, the data having a plurality of programs at the same time are transmitted on the data bus 5 in a multiplexed state. The data bus interface circuit 6 restores the data from the data bus 5 into the original data and supplies it to the storage medium 7. Accordingly, the storage medium 7 is able to record the program streams of a plurality of programs at the same time period.

Method for managing an instruction execution pipeline during debugging of a data processing system

Abstract: PROBLEM TO BE SOLVED: To provide a data processing system on an integrated circuit equipped with a microprocessor and a peripheral device together with an emulation unit for enabling the debug and emulation of integrated circuit at the time of connection to an external test system. SOLUTION: A microprocessor 1 has fetch/decode units 10a-10c and an instruction execution pipeline provided with plural execution stages related to the unit of function execution. Since the pipeline of microprocessor 1 is not protected, the waiting time of access to a data memory 22 and register files 20 (20a and 20b) can be utilized by a system program code stored in an instruction storage device 23. An emulation unit 50 performs operation through a method for avoiding any state such as the generation of unrelated operation to affect the memories 22-23 and peripheral devices 60-61 during emulation.

Content addressable memory having memory cells storing don't care states for address translation

Abstract: A method of accessing a content addressable memory storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state, is disclosed. The stored information is compared with a one bit signal. A match is indicated when the one bit signal represents a logic zero and the stored information represents the don't care state, or when the one bit signal represents a logic one and the stored information represents a don't care state. An absence of a match is indicated when the one bit signal represents a logic zero and the stored information represents an invalid state, or when the one bit signal represents a logic one and the stored information represents the invalid state. The content addressable memory is especially adapted for use in a translation buffer providing variable page granularity. The don't care state permits multiple virtual page numbers to match a single entry storing information for multiple physical pages. The invalid state eliminates the need for a dedicated valid bit in each entry.

Method of estimating power consumption of each instruction processed by a microprocessor

Abstract: This invention provides a method of estimating the power consumption of a microprocessor with the use of an instruction file that is simple and easy to prepare. A microprocessor (3, 4) reads instructions out of a main memory (2) or an instruction cache (1) and executes them. A group of instructions that include at least one target instruction whose power consumption is to be estimated is repeatedly executed in simulations, to find the power consumption of the microprocessor on the target instruction in a cache miss state, as well as the power consumption of the microprocessor on the target instruction in a cache hit state, according to the power consumption of the microprocessor in given cycles.

Field programmable gate array with integrated debugging facilities

Abstract: A number of enhanced logic elements (LEs) are provided to form a FPGA. Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved FPGA further comprises a network of crossbars, a context bus, a scan register, and a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated. Furthermore, the enhanced LEs may be used for "level sensitive" as well as "edge sensitive" circuit design emulations.