Showing papers on "State (computer science) published in 1998"

Nonvolatile multilevel memories for digital applications

Abstract: When thinking of semiconductor memories, it comes naturally to associate stored bits and memory cells with a one-to-one relationship. That, however, is not really a must nor necessarily the most convenient solution for data storage, since using analog signals and digital-to-analog (D/A) as well as analog-to digital (A/D) conversions a large number of bits could be memorized in a single cell, although, of course, the use of analog signals presents all drawbacks of signal-to-noise ratio that are so well known in electronics. In fact, the real question in this sense concerns the number of bits used for the A/D and D/A conversions, since the conventional (fully) digital case can be seen as the simplest realization of a general approach tending to infinitely precise analog storage (i.e. an infinite number of stored bits per cell) at the other extreme. Naturally, in the real world the conflicting aspects of density (measured in bits per cell) and noise immunity (in a general sense) should be traded off one against the other looking for optimum use of silicon area, of course depending on technology, architectures, circuits and reliability. From this point of view it is obvious that the fully digital approach based on the one-bit one-cell concept does not represent necessarily the best solution. Recently, this general question has assumed real and practical significance for nonvolatile memories, since devices storing two bits per cell are now being introduced on the market. At the same time, in a number of research labs a significant effort is currently being dedicated to the study of the limits and practical convenience of storage density considering the current state of the art in technology and circuit designs. This problem, however, presents a number of interacting aspects concerning cell concept, programming and reading schemes, and architectures and reliability that are of interest well beyond the field of nonvolatile memories, because they are ultimately dealing with the basic question of analog versus digital signals. In this contrast, the present paper considers the question of multilevel nonvolatile memories in all its interacting aspects, analyzing both the current state of the art and the future possibilities.

Understanding Java stack inspection

Abstract: Current implementations of Java make security decisions by searching the runtime call stack. These systems have attractive security properties, but they have been criticized as being dependent on specific artifacts of the Java implementation. The paper models the stack inspection algorithm in terms of a well understood logic for access control and demonstrates how stack inspection is a useful tool for expressing and managing complex trust relationships. We show that an access control decision based on stack inspection corresponds to the construction of a proof in the logic, and we present an efficient decision procedure for generating these proofs. By examining the decision procedure, we demonstrate that many statements in the logic are equivalent and can thus be expressed in a simpler form. We show that there are a finite number of such statements, allowing us to represent the security state of the system as a pushdown automaton. We also show that this automaton may be embedded in Java by rewriting all Java classes to pass an additional argument when a procedure is invoked. We call this security passing style and describe its benefits over previous stack inspection systems. Finally, we show how the logic allows us to describe a straightforward design for extending stack inspection across remote procedure calls.

Data groups: specifying the modification of extended state

Abstract: This paper explores the interpretation of specifications in the context of an object-oriented programming language with subclassing and method overrides. In particular, the paper considers annotations for describing what variables a method may change and the interpretation of these annotations. The paper shows that there is a problem to be solved in the specification of methods whose overrides may modify additional state introduced in subclasses. As a solution to this problem, the paper introduces data groups, which enable modular checking and rather naturally capture a programmer's design decisions.

System and method for verifying the integrity and authorization of software before execution in a local platform

Abstract: A method to verify integrity of information and selectively determine whether the information is authorized to be executed by the platform. The information is downloaded to a platform operating in a pre-boot operational state.

Method and apparatus for hibernation within a distributed data processing system

Abstract: A method and apparatus provides initializing a data processing system within a distributed data processing system. The data processing system receives data wherein the data is used to initialize the data processing system. The data processing system saves an image within the data processing system in a selected state after initialization of the data processing system, wherein the image is a saved image. The data processing system restores to the state using the saved image.

Programmable gate array

Abstract: An array includes a set of cells (21, 23, 25, 27, 29, 31). At least one of which includes a threshold gate (33, 35) having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero and less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

Method, system and computer program product for iterative distributed problem solving

Abstract: A method, system and computer program product for automated technical support in a computer network having a client machine and at least one server. The method begins by selecting a diagnostic map useful in gathering diagnostic data for evaluating a given technical problem requiring diagnosis and correction. The diagnostic map encapsulates a set of one or more methods that, upon execution, explore the client machine and gather data. The diagnostic map is then executed by a diagnostic engine to generate a data set indicative of a current operating state of the client machine. This data set is forwarded from the client machine to the server for analysis. Based on the analysis performed at the server node, the data gathering process is repeated at the client machine, iteratively, until given information is available to a user of the client machine to correct the given technical problem.

Method and apparatus for long term verification of digital signatures

Abstract: The time over which a digital signature can be verified is extended well beyond the expiration of any or all of the certificates upon which that signature depends. A “save state” approach is disclosed, in which an archive facility is used to store public key infrastructure (PKI) state, e.g. cryptographic information, such as certificates and certificate revocation lists (CRLs), in addition to non-cryptographic information, such as trust policy statements or the document itself. This information comprises all that is necessary to re-create the signature verification process at a later time. When a user wants to reverify the signature on a document, possibly years later, a long term signature verification (LTSV) server re-creates the precise state of the PKI at the time the document was originally submitted. The LTSV server restores the state, and the signature verification process executes the exact process it performed (or would have performed) years earlier. In another embodiment the strength of cryptography is combined with the proven resilience of (non-public key) technology and procedures currently associated with secure data stores by saving the PKI state for future reverification; and protecting the PKI state information from intrusion by maintaining it in a secure storage facility which is protected by services, such as firewalls, access control mechanisms, audit facilities, intrusion detection facilities, physical isolation, and network isolation.

Disk drive having data-guarding firmware

Abstract: A disk drive includes a disk defining a multiplicity of sectors. A method of operating the disk drive includes a step of providing a firmware-controlled state machine which can be in any of a plurality of states including an off-line in-progress state. While the state machine is in the off-line in progress state, the drive performs a firmware-controlled scan of the multiplicity of sectors. While performing the firmware-controlled scan, the drive identifies and repairs a marginal sector.

Programmable operational system for managing devices participating in a network

Abstract: A programmable operational system for managing devices participating in a network including a collection of notices, operation logic that filters the collection of notices based on at least one criteria and that generates at least one operation indicative of a state change of the network, and an automation engine that uses the at least one operation to perform at least one process in response one or more operations The collection of notices, generated by a plurality of routines, are indicative of the state of hardware, software, and user actions that comprise the network including the state or status of one or more of the devices participating in the network The operation logic may include an operation engine and one or more operational groups Each operational group may further include one or more operations, each including a filter and configuration information The operation logic may further generate at least one job and store the job into memory, where each job references an operation The operation logic invokes a helper process to facilitate execution of each operation by the automation engine Thus, the process executed in response to the one or more operations may be implemented to provide an appropriate response to changes in the network

Computer hibernation implemented by a computer operating system

Abstract: A computer in accordance with the invention includes volatile executable memory and non-volatile secondary storage. An operating system is stored on the secondary storage, and is loaded into executable memory during a computer boot process. The operating system includes a hibernate/awaken function that executes from the executable memory of the computer. The hibernate/awaken function saves the processor state and the executable memory state to the secondary storage prior to a computer power-down and subsequently restores the processor state and the executable memory state from the secondary storage after the computer power-down without rebooting the operating system.

Detecting data races in Cilk programs that use locks

Abstract: When two parallel threads holding no locks in common access the same memory location and at least one of the threads modifies the location, a “data race” occurs, which is usually a bug. This paper describes the algorithms and strategies used by a debugging tool, called the Nondeterminator-2, which checks for data races in programs coded in the Cilk multithreaded language. Like its predecessor, the Nondeterminator, which checks for simple “determinacy” races, the Nondeterminator-2 is a debugging tool, not a verifier, since it checks for data races only in the computation generated by a serial execution of the program on a given input. We give an algorithm, ALL-SETS, that determines whether the computation generated by a serial execution of a Cilk program on a given input contains a race. For a program that runs serially in time T , accesses V shared memory locations, uses a total of n locks, and holds at most k n locks simultaneously, ALL-SETS runs in O(nkT α(V;V )) time and O(nkV ) space, where α is Tarjan’s functional inverse of Ackermann’s function. Since ALL-SETS may be too inefficient in the worst case, we propose a much more efficient algorithm which can be used to detect races in programs that obey the “umbrella” locking discipline, a programming methodology that is more flexible than similar disciplines proposed in the literature. We present an algorithm, BRELLY, which detects violations of the umbrella discipline in O(kT α(V;V )) time using O(kV ) space. We also prove that any “abelian” Cilk program, one whose critical sections commute, produces a determinate final state if it is deadlock free and if it generates any computation which is datarace free. Thus, the Nondeterminator-2’s two algorithms can verify the determinacy of a deadlock-free abelian program running on a given input. Keywords

Synthesis of supervisory controllers for hybrid systems based on approximating automata

Abstract: The paper concerns the synthesis of supervisory controllers for a class of continuous-time hybrid systems with discrete-valued input signals that select differential inclusions for continuous-valued state trajectories and event-valued output signals generated by threshold crossings in the continuous state space, the supervisor is allowed to switch the input signal value when threshold events are observed. The objective is to synthesize a nonblocking supervisor such that the set of possible sequences of control and threshold event pairs for the closed-loop system lies between given upper and lower bounds in the sense of set containment. We show how this problem can be converted into a supervisor synthesis problem for a standard controlled discrete-event system (DES). A finite representation may not exist for the exact DES model of the hybrid system, however. To circumvent this difficulty, we present an algorithm for constructing finite-state Muller automata that accept outer approximations to the exact controlled threshold-event language, and we demonstrate that supervisors that solve the synthesis problem for the approximating automata achieve the control specifications when applied to the original hybrid system.

System and method for evaluating monitored computer systems

Abstract: A computer system used in monitoring another computer system provides both textual resolution information describing a likely solution for a problem encountered in the monitored computer system as well as component information that relates to the particular problem The component information includes the various hardware, software and operating conditions found in the monitored computer system The monitoring computer system determines if a condition of a predetermined severity exists in the monitored computer system according to diagnostic information provided from the monitored computer system The diagnostic information is represented in the monitoring computer system as a hierarchical representation of the monitored computer system The hierarchical representation provides present state information indicating the state of hardware and software components and operating conditions of the monitored computer system The resolution information relating to the condition is retrieved from a resolution database and relevant component information is retrieved from the hierarchical representation of the computer system and presented to a support engineer to assist them in diagnosing the problem in the monitored computer system

Content addressable memory

Abstract: A content addressable memory employs a word-sliced architecture, in order to localize word match logic, and a global data bus, to convey data between the memory input/output circuitry and the plurality of word slices. Timing information is embedded in the global data bus in the form of a model global data signal. This signal interacts with two major control signals to self-time the memory. The number of major control signals is such that all possible memory states are uniquely represented, but the memory cannot power-up in an invalid or unrecoverable state. Three model timing paths are used to match the delay of the self-timing loop with that of the actual operation: one each for READ, WRITE and SEARCH.

System and method for automatically maintaining a computer system

Abstract: A system and method for the automated maintenance of a computer system. A scheduler periodically activates sensors. When activated, the sensors gather information about various aspects of the computer system. The sensors store this information in a knowledge database. The knowledge database also contains cases, questions, and actions. The cases describe potential computer problems and solutions. The questions are used to diagnose the problems, while the actions describe steps that can be taken to solve the diagnosed problems. If the information gathered by the sensors indicates a problem with the computer system, then the sensors activate an artificial intelligence engine. The engine uses the information in the knowledge database to evaluate certain cases. If information necessary to evaluate a case is not in the knowledge database, then the engine activates a sensor to gather the information. As the cases are evaluated, the confidence levels of certain other cases, questions, and actions increase. If the confidence level of a case or question rises above a predetermined threshold, then the engine evaluates that case or question. If the confidence level of an action rises above the threshold, then that action represents the likely solution to the problem. Accordingly, the engine activates a sensor to perform the action. If no case, question, or action rises above the threshold, then the knowledge database does not contain enough information to solve the problem. In such a case, the engine saves the state of the computer system and knowledge database. Then, a human expert can update the database with the knowledge necessary to solve the problem.

Time-stamping with binary linking schemes

Abstract: We state the basic requirements for time-stamping systems applicable as the necessary support to the legal use of electronic documents. We analyze the main drawbacks of the time-stamping systems proposed to date and present a new system that meets all the stated requirements. We prove that these requirements cannot be significantly tightened.

Method and apparatus for increasing security against unauthorized write access to a protected memory

Abstract: A system and method for protecting a non-volatile storage element of an electronic system from an unauthorized write access is described. The method features the operational steps of entering a mode of operation in which an authentication process is performed, placing a security circuit of the electronic system in a first predetermined state of operation before leaving the mode of operation, checking the current state of the security circuit, and halting further operations of the electronic system if the security circuit exists in a state of operation other than the first predetermined state of operation.

System and method of using annotations to optimize dynamically translated code in the presence of signals

Abstract: A method and system of dynamically translating code that uses code annotations to determine whether the dynamic translator must fully materialize machine state. At compilation time, annotations are placed in an application's executable file indicating the number of formal parameters expected by each of the application's entry points. When the application is dynamically translated, the dynamic translation system (DTS) aggressively translates the application. Therefore, the DTS does not generate instructions for materializing the machine state at potential stopping points. When the application makes a system call that arms an exception handler, the DTS looks to the annotations to determine the number of formal parameters expected by the handler. If an exception handler expects two or fewer parameters, then that handler does not use the machine state. Conversely, if a handler expects three or more parameters, then that handler may use the machine state. Therefore, if the handler only has two formal parameters, then the DTS continues to aggressively translate the application program. Otherwise, the DTS discards all of the previously translated code and starts conservatively translating the application.

Using Magnatic Disk Instead of Main Memory in the Murphi Verifier

Abstract: In verification by explicit state enumeration a randomly accessed state table is maintained. In practice, the total main memory available for this state table is a major limiting factor in verification. We describe a version of the explicit state enumeration verifier Murϕ that allows the use of magnetic disk instead of main memory for storing almost all of the state table. The algorithm avoids costly random accesses to disk and amortizes the cost of linearly reading the state table from disk over all states in a given breadth-first level. The remaining runtime overhead for accessing the disk is greatly reduced by combining the scheme with hash compaction. We show how to do this combination efficiently and analyze the resulting algorithm. In experiments with three complex cache coherence protocols, the new algorithm achieves memory savings factors of one to two orders of magnitude with a runtime overhead of typically only around 15%.

Method of performing checkpoint/restart of a parallel program

Abstract: A checkpoint of a parallel program is taken in order to provide a consistent state of the program in the event the program is to be restarted. Each process of the parallel program is responsible for taking its own checkpoint, however, the timing of when the checkpoint is to be taken by each process is the responsibility of a coordinating process. During the checkpointing, various data is written to a checkpoint file. This data includes, for instance, in-transit message data, a data section, file offsets, signal state, executable information, stack contents and register contents. The checkpoint file can be stored either in local or global storage. When it is stored in global storage, migration of the program is facilitated. When a parallel program is to be restarted, each process of the program initiates its own restart. The restart logic restores the process to the state at which the checkpoint was taken.

Transparent Migration of Java-Based Mobile Agents

Abstract: In this paper we describe a way to save and restore the state of a running Java program. We achieve this on the language level, without modifying the Java virtual machine, by instrumenting the programmer’s original code with a preprocessor. The automatically inserted code saves the runtime information when the program requests state saving and reestablishes the program’s runtime state on restart. The current preprocessor prototype is used in a mobile agent scenario to offer transparent agent migration for Java based mobile agents, but could generally be used to save and reestablish the execution state of any Java program.

Method and system for supplying a custom software image to a computer system

Abstract: A method and system for supplying a software image to a computer system utilize a custom-programmed compact disk (CD) ROM that is configured for a specified individual computer system and constrained to be downloaded to and operable on only the specified individual computer system. The method and system further utilize an installation procedure for restoring the specified computer system to the software state that the computer was in at the time the computer left the factory after initial configuration and downloading. The custom-programmed CD ROM 106 is delivered to a customer in combination with a bootable flexible diskette 108, and an instructional technical instruction sheet for usage by the customer to restore the computer system to a “factory new” software condition.

Interpreter with virtualized interface

Abstract: A computer application program subsystem (100) includes a program interpreter (120) and an application program interface (API 110) through which an external program requests an execution of a program of interest, such as a macro, in a specified simulated environment The external program that requests the execution of the program of interest may further specify a simulated application state The program of interest is written in a program language that the interpreter can interpret The subsystem further includes an output path for returning to the external program at least one indication of what action or actions the program of interest would have taken if the program of interest had been run in a real environment that corresponds to the specified simulated environment The output path may be implemented using a callback function that is triggered upon the occurrence of an instruction of the program of interest satisfying at least one notification criterion, and/or upon the occurrence of the program of interest satisfying at least one termination criterion The methods and apparatus can be useful in detecting an occurrence of viral behavior in a macro by interpreting the macro in the specified virtual environment and virtual application state, and then notifying the external program when the macro performs some predetermined activity, such as writing data to some predetermined region of system memory

Control program tracking and display system

Abstract: Control program statements are graphically displayed as flowchart logic (42). The runtime engine (32) associated with the process control computer monitors (12) and maintains state data (65) indicating whether a program statement was executed on every pass, on at least one but not all passes. The user is thus provided with useful logic flow information (72) even though the executing program (62) may operate cyclically at a speed faster than the user can directly perceive.

Self regulating temperature/performance/voltage scheme for micros (X86)

Abstract: A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating The states are selected by a logic network based on information that is provided by temperature sensors and a performance control The logic network can be envisioned as an UP-DOWN counter The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant

Verifying Networks of Timed Processes (Extended Abstract)

Abstract: Over the last years there has been an increasing research effort directed towards the automatic verification of infinite state systems, such as timed automata, hybrid automata, data-independent systems, relational automata, Petri nets, and lossy channel systems. We present a method for deciding reachability properties of networks of timed processes. Such a network consists of an arbitrary set of identical timed automata, each with a single real-valued clock. Using a standard reduction from safety properties to reachability properties, we can use our algorithm to decide general safety properties of timed networks. To our knowledge, this is the first decidability result concerning verification of systems that are infinite-state in “two dimensions”: they contain an arbitrary set of (identical) processes, and they use infinite data-structures, viz. real-valued clocks. We illustrate our method by showing how it can be used to automatically verify Fischer's protocol, a timer-based protocol for enforcing mutual exclusion among an arbitrary number of processes.

Method and system of configuring a speech recognition system

Abstract: A speech control system and method is described, wherein a state definition information is loaded from a network application server. The state definition information defines possible states of the network application server and is used for determining a set of valid commands of the network application server, such that a validity of a text command obtained by converting an input speech command can be checked by comparing said text command with said determined set of valid commands. Thereby, a transmission of erroneous text commands to the network application server can be prevented so as to reduce total processing time and response delays.

Self-timed pipelined datapath system and asynchronous signal control circuit

Abstract: A self-timed pipelined datapath system reduces its power dissipation by accurately controlling the active and inactive states of the multi-threshold CMOS (MT-CMOS) circuit (11A) used as its combinational circuit. The MT-CMOS circuit comprises a logic circuit (1) of low-threshold and a power control circuit (2H, 2L) formed of high-threshold transistors for controlling the power feeding to the logic circuit. The self-timed pipelined datapath system comprising: a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit (11A) for processing input data and a register (REG1) connected to the input side of the combinational circuit (11A); and an asynchronous signal control circuit (13A) that controls data transmission to and from each of the registers in the pipelined datapath circuit in response to a request signal. The state change of an active state to an inactive state of the combinational circuit (11A) is performed in consideration of the signal propagation time therein, whereby the issue of the request signal (REQi) with respect to the combinational circuit (11A) at the preceding stage is delayed from the time the request signal with respect to the current combinational circuit is issued.

Programmable and flexible power management unit

Abstract: A programmable Power Management Unit (PMU) is provided. The Power Management Unit (PMU) supports a number of different power states namely a normal power state, a software-controlled sleep power sate, a hardware-controlled sleep power state, and two register programmable power states. In the normal power state, all circuits in the integrated circuit (e.g., graphics/display controller) are enabled. In the software-controlled sleep power state, all circuits in the integrated circuit are disabled except for frame buffer memory refresh logic and part of the bus interface. In the hardware-controlled sleep power state, all circuits in the integrated circuit are disabled except for the memory interface logic. In the two register programmable power states, circuits can be selectively powered up or down as desired in a single power sequencing. Moreover, under the present invention, the interval between circuits that are being disabled or enabled in a power sequencing is also programmable.