Showing papers on "State (computer science) published in 1999"

State models for monitoring processes

Abstract: A system and method for preparing, using and displaying a state model of a process, as an industrial or business process, as a sequence of discrete steps. The state model defines the behavior of the logical objects making up a process model of the process as a set of permitted states and a set of permitted transitions between the permitted states. The method involves creating a state model (61) with certain parameters, a Create/Modify State Transition for a State Model (63) and Associate State Transition with Rules and Conditions (65). These rules are inputted into a graphical user interface which causes appropriate rules to be extracted from a database (67). They are assembled into a state machine execution engine (69) and implemented (70) to produce an enforced state model on targeted business objects (71) and the target business object is enabled (73).

Symbolic Verification of Communication Protocols with Infinite StateSpaces using QDDs

Abstract: We study the verification of properties of communication protocols modeled by a finite set of finite-state machines that communicate by exchanging messages via unbounded FIFO queues. It is well-known that most interesting verification problems, such as deadlock detection, are undecidable for this class of systems. However, in practice, these verification problems may very well turn out to be decidable for a subclass containing most “real” protocols. Motivated by this optimistic (and, we claim, realistic) observation, we present an algorithm that may construct a finite and exact representation of the state space of a communication protocol, even if this state space is infinite. Our algorithm performs a loop-first search in the state space of the protocol being analyzed. A loop-first search is a search technique that attempts to explore first the results of successive executions of loops in the protocol description (code). A new data structure named Queue-content Decision Diagram (QDD) is introduced for representing (possibly infinite) sets of queue-contents. Operations for manipulating QDDs during a loop-first search are presented. A loop-first search using QDDs has been implemented, and experiments on several communication protocols with infinite state spaces have been performed. For these examples, our tool completed its search, and produced a finite symbolic representation for these infinite state spaces.

On-chip logic analysis and method for using the same

Abstract: A programmable logic device (PLD) includes a plurality of logic resources, a plurality of multi-bit configuration memories (MBCMs), and a trigger logic structure. The plurality of MBCMs include multiple memory slices that allow the PLD to switch rapidly between configurations, or contexts. In one embodiment, at least one memory slice configures the PLD into a logic analysis context for providing on-chip testing. In one embodiment, the plurality of logic resources include a plurality of storage elements. State data generated by a user-defined context is stored in the plurality of storage elements. When the trigger logic structure provides a trigger signal, the PLD is reconfigured into the logic analysis context. The logic analysis context reads and processes the state data stored in the plurality of storage elements to test the performance of the user-defined context. In one embodiment, the storage elements are multi-bit micro-registers that store state data generated by a plurality of contexts implemented in the multiple-context PLD.

System and method for cross-platform application level power management

Abstract: A framework for the development of applications which manage the power resources and power states of power-manageable computer systems and attached devices. In one embodiment, the power management framework comprises a plurality of Java™ programming interfaces (APIs) which are part of the Java™ Platform. Therefore, the same framework is configured to enable the same power-aware Java™ applications to execute on many different computing platforms, operating systems, and computer hardware. The programming interfaces comprise a system-level programming interface, a notification programming interface, an exception programming interface, and a device-level programming interface. The system-level programming interface permits Java™ applications to obtain a current system power state and, with the proper privilege, to influence the current system power state. The notification programming interface permits Java™ applications to be notified regarding transitions from one system power state to another system power state. The exception programming interface permits Java™ applications to be notified regarding errors in power management. The device-level programming interface permits Java™ applications to obtain a current device power state and, with the proper privilege, to influence the current device power state. The power management framework defines a plurality of standardized system power states, standardized device power states, and power state transitions.

Implantable device with digital waveform telemetry

Abstract: A technique for acquiring and accessing information from a medical implantable device is provided. Analog waveforms of interest are sensed and processed by signal acquisition circuitry. Analog parameters of interest are applied to selector switches which are controlled by a logic circuit. The logic circuit is also coupled an A/D converter for converting the analog signals to digital values. The digital values are stored in dedicated registers and are available for telemetry to an external device upon receipt of a request or prompt signal. When a digitized value is accessed and telemetered, the control logic circuit changes the conductive state of the selector switches to apply the corresponding analog signal to the A/D converter. The resulting digital value is applied to the corresponding register to refresh the accessed and telemetered value. The technique permits the external device to request and configure the implanted device to send only digitized values of interest. The technique also makes efficient use of the A/D converter, which consumes energy only as needed to refresh the memory when digital values are accessed and telemetered.

On the capacity of generalized write-once memory with state transitions described by an arbitrary directed acyclic graph

Abstract: The generalized write-once memory introduced by Fiat and Shamir (1984) is a q-ary information storage medium. Each storage cell is expected to store one of q symbols, and the legal state transitions are described by an arbitrary directed acyclic graph. This memory model can be understood as a generalization of the binary write-once memory which was introduced by Rivest and Shamir (1982). During the process of updating information, the contents of a cell can be changed from a 0-state to a 1-state but not vice versa. We study the problem of reusing a generalized write-once memory for T successive cycles (generations). We determine the zero-error capacity region and the maximum total number of information hits stored in the memory for T consecutive cycles for the situation where the encoder knows and the decoder does not know the previous state of the memory. These results extend the results of Wolf, Wyner, Ziv, and Korner (1984) for the binary write-once memory.

Analysis of Hybrid Systems: An Ounce of Realism Can Save an Infinity of States

Abstract: Hybrid automata have been introduced in both control engineering and computer science as a formal model for the dynamics of hybrid discrete-continuous systems In the case of so-called linear hybrid automata this formalization supports semi-decision procedures for state reachability, yet no decision procedures due to inherent undecidability [4] Thus, unlike finite or timed automata, already linear hybrid automata are out-of-scope of fully automatic verification In this article, we devise a new semi-decision method for safety of linear and polynomial hybrid systems which may only fail on pathological, practically uninteresting cases These remaining cases are such that their safety depends on the complete absence of noise, a situation unlikely to occur in real hybrid systems Furthermore, we show that if low probability effects of noise are ignored akin to the way they are suppressed in digital modelling then safety becomes fully decidable

Infinite State Model Checking by Abstract Interpretation and Program Specialisation

Abstract: We illustrate the use of logic programming techniques for finite model checking of CTL formulae. We present a technique for infinite state model checking of safety properties based upon logic program specialisation and analysis techniques. The power of the approach is illustrated on several examples. For that, the efficient tools logen and ecce are used. We discuss how this approach has to be extended to handle more complicated infinite state systems and to handle arbitrary CTL formulae.

An Object-Oriented Effects System

Abstract: An effects systems describes how state may be accessed during the execution of some program component. This information is used to assist reasoning about a program, such as determining whether data dependencies may exist between two computations. We define an effects system for Java that preserves the abstraction facilities that make object-oriented programming languages attractive. Specifically, a subclass may extend abstract regions of mutable state inherited from the superclass. The effects system also permits an object's state to contain the state of wholly-owned subsidiary objects. In this paper, we describe a set of annotations for declaring permitted effects in method headers, and show how the actual effects in a method body can be checked against the permitted effects.

Finite state machine synthesis with concurrent error detection

Abstract: A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are checked independently. By checking parity on the present state instead of the next state, this technique allows detection of errors in bistable elements (that were hitherto not detected by many previous techniques) while requiring no changes in the original machine specifications. This paper also examines design choices with respect to parity prediction circuits. Two such examined choices are the multi-parity-group and the single-parity-group techniques. A new state encoding technique based on the JEDI program is developed for the synthesis of the next-state logic with an additional parity output. Synthesis results produced by our proposed procedure for the MCNC'89 FSM benchmark circuits show on average a 25% reduction in literal counts compared to previous techniques.

Graphical user interface that displays operation of processor threads over time

Abstract: A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding to one of the threads.

Balanced cryptographic computational method and apparatus for leak minimization in smartcards and other cryptosystems

Abstract: Cryptographic devices that leak information about their secrets through externally monitorable characteristics (such as electromagnetic radiation and power consumption) may be vulnerable to attack, and previously-known methods that could address such leaking are inappropriate for smartcard and many other cryptographic applications. Methods and apparatuses are disclosed for performing computations in which the representation of data, the number of system state transitions at each computational step, and the Hamming weights of all operands are independent of computation inputs, intermediate values, or results. Exemplary embodiments (figure 6) implemented using conventional hardware elements such as electronic components (611, 613) and logic gates (610, 620, 630, 640) as well as software executing on conventional microprocessors are described.

Demand based generation of symbolic information

Abstract: A human-oriented object programming system (HOOPS) and its debugger provide an interactive and dynamic modeling system to assist in the incremental generation of symbolic information of computer programs that facilitates the development of complex computer programs such as operating systems and large applications with graphic user interfaces (GUIs). A program is modeled as a collection of units called components. A component represents a single compilable language element such as a class or a function. One major functionality built in HOOPS is the debugger, using symbolic properties. The database stores the components and properties. The debugger, using a GUI, displays to the user the execution state of the program. To display the execution state in terms of the programmer's source code, the debugger demands retrieval and/or generation of the symbolic properties of the program. The compiler, which is responsible for calculating the dependencies associated with a component, uses those dependencies to generate the information stored in symbolic properties. The debugger matches versions of source and object code and retrieves source code configuration as needed. Symbolic properties that are stored in the database can be removed to reduce database and disk memory usage; they can be later reconstructed using the same method of demand-based generation of symbolic information.

A partial order approach to branching time logic model checking

Abstract: Partial order techniques enable reducing the size of the state space used for model checking, thus alleviating the “state space explosion” problem. These reductions are based on selecting a subset of the enabled operations from each program state. So far, these methods have been studied, implemented, and demonstrated for assertional languages that model the executions of a program as computation sequences, in particular the linear temporal logic. The present paper shows, for the first time, how this approach can be applied to languages that model the behavior of a program as a tree. We study here partial order reductions for branching temporal logics, e.g., the logics CTL and CTL* (with the next time operator removed) and process algebra logics such as Hennesy–Milner logic (withτactions). Conditions on the selection of subset of successors from each state during the state-space construction, which guarantee reduction that preserves CTL* properties, are given. The experimental results provided show that the reduction is substantial.

Safe and protected execution for the Morph/AMRM reconfigurable processor

Abstract: Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase performance. In the Morph/AMRM system we are exploring the addition of reconfigurable logic, deeply integrated with the processor core, employing the reconfigurability to manage the cache, datapath, and pipeline resources more effectively. However, integration of reconfigurable logic introduces significant protection and safety challenges for microprocess execution. We analyze the protection structures in a state of the art microprocessor core (R10000), identifying the few critical logic blocks and demonstrating that the majority of the logic in the processor core can be safely reconfigured. Subsequently, we propose a protection architecture for the Morph/AMRM reconfigurable processor which enable nearly the full range of power of reconfigurability in the processor core while requiring only a small number of fixed logic features which to ensure safe, protected multiprocess execution.

System and method for managing a plurality of processor performance states

Abstract: In a computer system having a processor capable of operating at a plurality of performance states, wherein each of the plurality of performance states has an expected processing performance, a system and method is described for switching between the plurality of performance states. A determination is made that a performance state change is needed. The system waits for the processor to enter a quiescent state and, when the processor enters the quiescent state, places the processor in the new performance state.

Automated system recovery via backup and restoration of system state

Abstract: A method and system for backing up and restoring a system that cannot reboot in an automatic and efficient manner. A backup component copies and stores the state that defines the configuration of the computer system by obtaining and preserving the underlying description of the system. The backed-up state information includes the disk structure and layout. Also backed up is the information specifying what to execute during restore phases, including programs to copy and execute, any error handling, and any special driver files to load. A restore component operates in a first phase to use the backed-up configuration information to compare with the current state of a new system, and the disk and volume state are restored according to the saved information. Once the underlying system state is restored, an environment is created by copying a set of files required to run the programs that will restore the remainder of the data. A second restore phase configures the environment for launching a restore program by detecting and installing drivers and support for devices installed on the system. The restore program or programs are then run according to the instructions that were saved therewith during the backup phase, to restore the remainder of the data.

Copy generation management method, information signal reproducing method, information signal reproducing apparatus, and information signal recording apparatus

Abstract: A reproducing and/or recording system in which copy generation of an information signal is controlled through the use of copy control information that is added to the information signal. The copy control information takes on at least one of three possible states, a one-copy allowed state, a more-copy prohibited state and a copy absolutely prohibited state. The system determines an initial copy control state for the signal being reproduced and determines the state of copy control information to be added to the reproduced signal based on at least the initial copy control information. During recording it may be determined that no further copy control information is to be added to the signal.

Program/erase endurance of EEPROM memory cells

Abstract: A circuit and method increases the endurance of memory cells in a memory array by decreasing the number of times a memory cell is programmed or erased. A bit-wise program/erase controller coupled to the memory array modifies the erasing and programming of multi-bit data words by erasing only those memory cells which must be erased and programming only those memory cells which must be programmed. Specifically, the bit-wise program/erase controller compares a new data word, which will be written into the memory array at a write address, with the current data word at the write address. The memory cells at the write address are categorized into a first subset and a second subset. The first subset of memory cells are currently in a programmed state but must be erased because the corresponding bit of the new data word is at an erased logic level. The second subset of memory cells are currently in an erased state but must be programmed because the corresponding bit of the new data word is at a programmed logic level. Bit-wise program/erase controller erases only the first subset of memory cells and programs only the second subset of memory cells. Thus, over multiple writes into the memory array, the number times each memory cell is erased or programmed is reduced resulting in greater endurance of the memory cells.

Thermal control within systems having multiple CPU performance states

Abstract: In a computer system having a processor capable of operating at a plurality of performance states, wherein the plurality of performance states includes a low power state and a high performance state and wherein user threads are executable at each of the performance states, a system and method of controlling heat generated by the computer system. A thermal threshold is set. The system enters the high performance state and begins executing user threads. If, while in high performance state, a determination is made that the thermal threshold is exceeded, a transition is made to a low power state.

Binary state machine system and method for REGEX processing of a data stream in an intrusion detection system

Abstract: A binary state machine system and method for REGEX processing of a data stream in an intrusion detection system are disclosed. The method comprises maintaining a state table. The state table is indexed such that inputs comprising a current state and a current character yield an output of a new state. The new state is related to an indication of an attack on a computer network. The method further includes maintaining the current state. An input stream comprising a plurality of characters is received. A first character of the input stream is selected as the current character. The current character and the current state are compared to the state table to generate a new state.

Apparatus and method for tracing microprocessor instructions

Abstract: A microprocessor implements an instruction tracing mechanism that saves the state of the microprocessor without special hardware. Prior to the execution of a traced instruction, a trace microcode routine is implemented that saves the state of the microprocessor to external memory. The state information saved by the trace microcode routine varies depending upon the amount of data needed by the end user. After the state of the processor has been saved, the trace instruction is executed. State information that changed during the execution of the trace instruction is saved to memory prior to a subsequent instruction. The trace instruction mechanism advantageously requires minimal special hardware and expedites the saving of the processor state information.

Information communication robot device, information communication method and information communication robot system

Abstract: PROBLEM TO BE SOLVED: To provide an information communication robot device, information communication method and information communication robot system for performing the output of the information corresponding to the condition of health of a user and an action. SOLUTION: This information communication robot device comprises an attachable/detachable user state corresponding program plate-like memory 2 for storing the information corresponding to the state of an external user, an external input part 6 and output part 10 for inputting user detection information with the user and outputting the output information corresponding to the user state corresponding information and feedback information to the user, and a communication data generating/analyzing means 13 for analyzing the input user detection information and generating the feedback information and output information on the basis of the user state information and user detection information, so that the output information corresponding to the user detection information is outputted to the user, or a movable part is operated.

Automatically generating a program

Abstract: A method, an apparatus and a computer program product are described for automatically generating a state-based program for a component of a system consisting of a plurality of components communicating with each other, wherein the program is generated from a specification of the system, the specification comprising interaction-based sequence descriptions of the system. According to the present invention, all sequence descriptions of said component are determined, the sequence descriptions are normalized, a state-based specification of said component is determined from the normalized sequence descriptions, and the state-based program for the component is determined from the state-based specification. The present invention facilitates the process of program development since the costly, manual development of a state-based program from the specification of a system is automated at least to a substantial degree.

Dynamic creation of workflows from deterministic models of real world processes

Abstract: A workflow generated from a declarative model of a real world process represents the procedural steps to accomplish the process. In one embodiment, the declarative model may include a first number of state nodes and a second number of task nodes interconnected with the state nodes. In such cases, generating a workflow may be accomplished by choosing one of a number of paths through th emodel, each of the paths comprising an alternating series of one or more of the state nodes and one or more of the task nodes with any predecessor state node in one of the paths representing a precondition for a subsequent task node along the one of the paths and any following state node of the subsequent task node along the one of the paths representing a result of applying one or more actions that correspond to that task node. As part of a computer assisted scheduling system, the model may be configured to receive updates reflecting changes in the real-world manufacturing environment. Such changes may represent completed tasks, and/or a change in the availability of one or more resources represented in the model.

Quick starting for microprocessor-based system by retrieving a target state memory image and a target state data structure from an image storage medium

Abstract: A system and method for restoring a microprocessor-based system to a previously booted target state in which an image of memory and the processor registers in the previously booted state is saved and stored in a storage device. A restore routine executing in ROM retreives the image from the storage device and restores the system memory and processor registers to the target state. A operating system return routine then returns control of the system to the operating system software. In an exemplary implementation, a system in accordance with the invention is incorporated into a microprocessor-based external programmer for a cardiac rhythm management device in order to allow quick starting of the programmer from a powered down condition without going through a time consuming boot process.

Method of and apparatus for controlling supply of power to a peripheral device in a computer system

Abstract: A peripheral device, such as a data storage device, is employed in a computer system having one or more computers. The computer system includes an interface architecture, such as Fiber channel or Serial Storage Architecture (SSA), providing a continuously clocked serial link. The data storage device includes a power supply and data storage components, such as disk drives, carried in a housing. One or more data communication interfaces, each of which is adapted for coupling with a computer through conductors, are carried on the housing and coupled to the data storage components. The data storage components have a substantially powered up state and a substantially powered down state which is entered in response to a power down signal. Detector circuitry is operative to detect a clock signal loss at each one of the data communication interfaces and to produce the power down signal responsive to the detection.

Method and apparatus for automatically optimizing execution of a computer program

Abstract: The claimed invention can be used to automatically determine what files are needed to optimally execute a computer program to a desired state. In one embodiment the invention automatically creates an optimized file containing the files that are necessary to reach the desired state of a computer program. One or more remainder files may also be created. A remainder file contains the files that may be used by the computer program after reaching the desired state of execution.

State of statistical data editing and current research problems

Abstract: 1. INTRODUCTION This paper is my description of the state of statistical data editing and current research problems. It is not intended to be a complete description of all areas. Rather, it represents sub-areas of statistical data editing that I will describe in sufficient detail so that the discussion of a few research problems is more easily understood. I define statistical data editing (SDE) as those methods that are used to edit (i.e., clean-up) and impute (fill-in) missing or contradictory data. The end result of SDE is data that can be used for intended analytic purposes. These include primary purposes such as estimation of totals and subtotals for publications that are free of self-contradictory information. The published totals do not contradict published totals in other sources. Self-contradictory information might include groups of items that do not add to desired subtotals or totals for subgroups that exceed a known proportion of the total for the entire group. The uses of the data after SDE might be preparation of variances of estimates for a number of sub-domains and micro-data analyses. If only a few published totals need to be accurate, then an efficient use of resources may be to perform detailed edits on only a few records that effect the estimated totals. If many analyses need to be performed on a large number of sub-domains or if the full set of accurate micro-data are needed, then a very large number of edits, follow-up, and corrections may be needed. SDE can be used in all phases of survey processing. These phases include frame development, form design, proposed analytic purposes for which the data are collected, and quality assurance. This paper focuses primarily on SDE as it applies to analytic purposes, and places most emphasis on those procedures typically applied after the initial receipt of survey or other data. The main goal of SDE might be improved procedures and greater automation to enhance the ability of survey managers and analysts to provide accurate published estimates and micro-data. I broadly subdivide statistical data editing into two subcategories: (1) Fellegi-Holt (FH) methods and systems and (2) General methods and systems. FH systems are based on the Fellegi-Holt model of editing and typically add various options for imputation. General methods are all other methods. Whereas the paper by Fellegi and Holt (1976) appeared quite awhile ago, few systems have been implemented because of the difficulty in developing …